![DCLK](/images/new-backgrounds/22115/2211521x1.webp)
Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA =
Parameter | Symbol | Test Condition | Min | Typ | Max | Unit |
|
|
|
|
|
|
|
DCLK Cycle Time | tDCT |
| 26 | — | 1000 | ns |
DCLK Pulse Width High | tDCH |
| 10 | — | — | ns |
DCLK Pulse Width Low | tDCL |
| 10 | — | — | ns |
DFS | tSU:DFS |
| 5 | — | — | ns |
DFS Hold Time from DCLK Rising Edge | tHD:DFS |
| 5 | — | — | ns |
DOUT Propagation Delay from DCLK Falling | tPD:DOUT |
| 0 | — | 12 | ns |
Edge |
|
|
|
|
|
|
DCLK
DFS
DOUT
tDCH | tDCL |
| tDCT |
| tPD:OUT |
tHD:DFS
tSU:DFS |
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0 | 11 |