Silicon Laboratories SI4734/35-B20 manual Si4734/35-B20, Sclk Sen Sdio

Si4734/35-B20

Table 6. 3-Wire Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter						Symbol	Test Condition	Min	Typ	Max	Unit
SCLK Frequency						fCLK		0	—	2.5	MHz
SCLK High Time						tHIGH		25	—	—	ns
SCLK Low Time						tLOW		25	—	—	ns
SDIO Input,					to SCLK↑ Setup	tS		20	—	—	ns
				SEN
SDIO Input to SCLK↑ Hold						tHSDIO		10	—	—	ns
	Input to SCLK↓ Hold					tHSEN		10	—	—	ns
SEN
SCLK↑ to SDIO Output Valid						tCDV	Read	2	—	25	ns
SCLK↑ to SDIO Output High Z						tCDZ	Read	2	—	25	ns
SCLK,			SDIO, Rise/Fall time			tR, tF		—	—	10	ns
		SEN,

Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST.

SCLK

SEN

SDIO

70%

30%

70%

30%

70%

30%

tR tF

tS

tS

A6-A5,

A7 R/W,

A4-A1

Address In

tHSDIO

A0

tHIGH tLOW tHSEN

D15 D14-D1 D0

Data In

SCLK

70%

30%

Figure 4. 3-Wire Control Interface Write Timing Parameters

SEN

SDIO

70%

30%

70%

30%

tS

tS

A6-A5,

A7 R/W,

A4-A1

Address In

tHSDIO tCDV tHSEN

A0	D15	D14-D1	D0
½ Cycle Bus		Data Out
Turnaround

tCDZ

Figure 5. 3-Wire Control Interface Read Timing Parameters

Rev. 1.0 9