Ultra Fast USB 2.0 Multi-Slot Flash Media Controller

 

 

 

 

Datasheet

Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

128-PIN

BUFFER

 

 

NAME

SYMBOL

VTQFP

TYPE

DESCRIPTION

 

 

 

 

 

 

 

SM Busy or Data

SM_nB/R

56

IPU

This pin is connected to the BSY/RDY pin of

 

Ready

 

 

 

the SM device.

 

 

 

 

 

When using the internal FET, this pin has an

 

 

 

 

 

internal weak pull-up resistor that is tied to

 

 

 

 

 

the output of the internal Power FET, and is

 

 

 

 

 

controlled by the SM_PU bit of the

 

 

 

 

 

SMC_CTL register.

 

 

 

 

 

If an external FET is used (Internal FET is

 

 

 

 

 

disabled), then the internal pull-up is not

 

 

 

 

 

available (external pull-ups must be used).

 

 

 

 

 

 

 

SM Chip Enable

SM_nCE

54

O12PU

This pin is the active low chip enable signal

 

 

 

 

 

to the SM device.

 

 

 

 

 

When using the internal FET, this pin has an

 

 

 

 

 

internal weak pull-up resistor that is tied to

 

 

 

 

 

the output of the internal Power FET, and is

 

 

 

 

 

controlled by the SM_PU bit of the

 

 

 

 

 

SMC_CTL register.

 

 

 

 

 

If an external FET is used (Internal FET is

 

 

 

 

 

disabled), then the internal pull-up is not

 

 

 

 

 

available (external pull-ups must be used).

 

 

 

 

 

 

 

SM Card

GPIO14

57

I/O12

This is a GPIO designated as the Smart

 

Detection GPIO

(SM_nCD)

 

 

Media card detection pin.

 

 

 

 

 

 

 

 

 

MEMORY STICK INTERFACE

 

 

 

 

 

 

 

MS Bus State

MS_BS

91

O12

This pin is connected to the BS pin of the MS

 

 

 

 

 

device.

 

 

 

 

 

It is used to control the Bus States 0, 1, 2

 

 

 

 

 

and 3 (BS0, BS1, BS2 and BS3) of the MS

 

 

 

 

 

device.

 

 

 

 

 

 

 

MS Card

GPIO12

98

IPU

This is a GPIO designated as the Memory

 

Insertion GPIO

(MS_INS)

 

 

Stick card detection pin.

 

 

 

 

 

 

 

MS System CLK

MS_SCLK

101

O12

This pin is an output clock signal to the MS

 

 

 

 

 

device.

 

 

 

 

 

The clock frequency is software configurable.

 

 

 

 

 

 

 

MS System Data

MS_D[7:1]

100

I/O12PD

MS_D[7:0]: These pins are the bi-directional

 

In/Out

 

97

 

data signals for the MS device. MS_D2 and

 

 

 

93

 

MS_D3 have weak pull-down resistors.

 

 

 

95

 

MS_D1 has a pull down resistor if it is in

 

 

 

99

 

parallel mode, otherwise it is disabled. In 4-

 

 

 

96

 

or 8-bit parallel mode, there is a weak pull-

 

 

 

92

 

down resistor on all MS_D7~0 signals. The

 

 

 

 

 

resistors are controlled by MSC_SYSTEM_0,

 

 

 

 

 

MSC_MODE_CTL and MSC_PRO_HG

 

 

 

 

 

registers.

 

 

 

 

 

 

 

Revision 1.1 (05-29-08)

14

SMSC USB2250/50i/51/51i

DATASHEET