Ultra Fast USB 2.0
Datasheet
Table 5.1 USB2250/50i/51/51i
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NAME | SYMBOL | VTQFP | TYPE | DESCRIPTION |
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Memory Address | MA1[1:0] / | 25 | O12 | MA[1:0]: These signals address memory |
Bus | CLK_ | 27 |
| locations within the external memory. |
| SEL1[1:0] |
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| I/O12PD | CLK_SEL[1:0]: During nRESET assertion, | |
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| these pins will select the operating frequency |
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| of the external clock, and the corresponding |
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| weak |
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| nRESET is negated, the value on these pins |
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| will be internal latched and these pins will |
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| revert to MA[1:0] functionality; the internal |
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| CLK_SEL[1:0] = '00'. 24MHz |
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| CLK_SEL[1:0] = '01'. RESERVED |
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| CLK_SEL[1:0] = '10'. RESERVED |
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| CLK_SEL[1:0] = '11'. 48MHz |
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| Note: If the latched value is '1', then the |
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| corresponding MA pin is |
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| when the chip is in the powerdown |
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| state. |
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| If the latched value is '0', then the |
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| corresponding MA pin will function identically |
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| to the MA[15:3] pins at all times (other than |
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| during nRESET assertion). |
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Memory Write | nMWR | 3 | O12 | Program Memory Write; active low |
Strobe |
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Memory Read | nMRD | 115 | O12 | Program Memory Read; active low |
Strobe |
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Memory Chip | nMCE | 26 | O12 | Program Memory Chip Enable; active low. |
Enable |
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| This signal is asserted when any external |
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| access is being done by the processor. |
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| This signal is held to the logic 'high' while |
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| nRESET is asserted. |
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| MISC |
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General Purpose | LED1 / GPIO1 | 120 | I/O12 | GPIO: This pin may be used either as input, |
I/O |
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| edge sensitive interrupt input, or output. |
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| LED: In addition, as an output, the GPIO1 |
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| can be used output controlled by the |
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| LED1_GPIO1 register. |
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General Purpose | GPIO3 | 121 | I/O12 | This pin may be used either as input, edge |
I/O | (VBUS_DET) |
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| sensitive interrupt input, or output. |
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| This pin is not 5V tolerant. An external |
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| resistor divider must be used when |
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| connected to VBUS. |
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SMSC USB2250/50i/51/51i | 17 | Revision 1.1 |
DATASHEET