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| Ultra Fast USB 2.0 | |
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| Datasheet | |
Table 5.1 USB2250/50i/51/51i | |||||
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| BUFFER |
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NAME | SYMBOL | VTQFP | TYPE | DESCRIPTION |
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Crystal | XTAL1 | 124 | ICLKx | 24MHz Crystal or external clock input. |
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Input/External | (CLKIN) |
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| XTAL: This pin can be connected to one |
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Clock Input |
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| terminal of the crystal or it can be connected |
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| to an external 24/48MHz clock when a |
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| crystal is not used. |
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| Note: The MA[1:0] pins will be sampled |
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| while nRESET is asserted, and the |
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| value will be latched upon nRESET |
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| negation. This will determine the |
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| clock source and value. |
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Crystal Output | XTAL2 | 123 | OCLKx | 24MHz Crystal. |
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| This is the other terminal of the crystal, or it |
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| is left open when an external clock source is |
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| used to drive XTAL1(CLKIN). It may not be |
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| used to drive any external circuitry other than |
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| the crystal circuit. |
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1.8V PLL Power | VDD18PLL | 125 |
| This pin is the 1.8V Power for the PLL. |
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| If the internal regulator is enabled, then this |
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| pin must have a 1.0μF (or greater) ±20% |
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| (ESR <0.1Ω) capacitor to VSS. |
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3.3V Analog | VDDA33 | 128 |
| 3.3V Analog Power |
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Power |
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| MEMORY / IO INTERFACE |
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Memory Data | MD[7:0] | 33 | I/O12 | These signals are used to transfer data |
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Bus |
| 29 |
| between the internal CPU and the external |
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| 30 |
| program memory. |
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| 31 |
| Note: These pins have internal weak pull- |
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| 34 |
| up resistors that are controlled by |
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| 35 |
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| the MD_PU_DIS bit of the |
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| 36 |
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| PWR_MGMT_CTL1 register. |
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| 37 |
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Memory Address | MA16 | 28 | O12 | These signals address memory locations |
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Bus |
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| within the external memory. MA16 is a bit |
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| generated by the ROM Mapper. |
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Memory Address | MA[15:2] | 2 | O12 | These signals address memory locations |
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Bus |
| 4 |
| within the external memory. |
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| 107 |
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| 1 |
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| 113 |
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| 24 |
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| 111 |
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| 109 |
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| 106 |
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| 108 |
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| 110 |
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| 112 |
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| 114 |
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| 116 |
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Revision 1.1 | 16 | SMSC USB2250/50i/51/51i |
DATASHEET