Ultra Fast USB 2.0 Multi-Slot Flash Media Controller

 

 

 

 

Datasheet

Table 5.1 USB2250/50i/51/51i 128-Pin VTQFP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

128-PIN

BUFFER

 

 

NAME

SYMBOL

VTQFP

TYPE

DESCRIPTION

 

 

 

 

 

 

 

General Purpose

GPIO4

118

I/O12

GPIO: This pin may be used either as input,

 

I/O

(SCL/xD_ID)

 

 

edge sensitive interrupt input, or output.

 

 

 

 

 

 

 

 

 

 

O12

SCL: This is the clock output when used with

 

 

 

 

 

an external EEPROM.

 

 

 

 

 

 

 

 

 

 

I/O12

xD_ID: This is the xD card detection pin only

 

 

 

 

 

applicable to the USB2250/USB2250i.

 

 

 

 

 

 

 

General Purpose

GPIO5

5

I/O12

This pin may be used either as input, edge

 

I/O

(SDA)

 

 

sensitive interrupt input, or output.

 

 

 

 

 

SDA: This is the data pin when used with an

 

 

 

 

 

external serial EEPROM.

 

 

 

 

 

 

 

General Purpose

GPIO8 /

14

I/O12

GPIO: This pin may be used either as input,

 

I/O

CRD_PWR0

 

 

edge sensitive interrupt input, or output.

 

 

 

 

 

 

 

 

 

 

I/O200

CRD_PWR: Card Power drive of 3.3V @

 

 

 

 

 

either 100mA or 200mA.

 

 

 

 

 

 

 

General Purpose

GPIO9 /

78

I/O12

GPIO: This pin may be used either as input,

 

I/O

CRD_PWR1

 

 

edge sensitive interrupt input, or output.

 

 

 

 

 

 

 

 

 

 

I/O200

CRD_PWR: Card Power drive of 3.3V @

 

 

 

 

 

either 100mA or 200mA.

 

 

 

 

 

 

 

General Purpose

GPIO10 /

76

I/O12

GPIO: These pins may be used either as

 

I/O

CRD_PWR2

 

 

input, edge sensitive interrupt input, or

 

 

 

 

 

output. It is a requirement that this is the

 

 

 

 

 

only FET used to power SM devices. Failure

 

 

 

 

 

to do this will violate SM voltage specification

 

 

 

 

 

on SM device pins.

 

 

 

 

 

 

 

 

 

 

I/O200

CRD_PWR: Card Power drive of 3.3V @

 

 

 

 

 

either 100mA or 200mA.

 

 

 

 

 

 

 

General Purpose

GPIO11 /

16

I/O12

GPIO: These pins may be used either as

 

I/O

CRD_PWR3

 

 

input, edge sensitive interrupt input, or

 

 

 

 

 

output.

 

 

 

 

 

 

 

 

 

 

I/O200

CRD_PWR: Card Power drive of 3.3V @

 

 

 

 

 

either 100mA or 200mA.

 

 

 

 

 

 

 

RESET Input

nRESET

64

IS

This active low signal is used by the system

 

 

 

 

 

to reset the chip. The active low pulse should

 

 

 

 

 

be at least 1μs wide.

 

 

 

 

 

 

 

TEST Input

TEST

103

I

This signal is used for testing the chip. User

 

 

 

 

 

should normally tie this pin low externally, if

 

 

 

 

 

the test function is not used.

 

 

 

 

 

 

 

Regulator

REG_EN

6

IPU

This signal is used to enable the internal

 

Enable

 

 

 

1.8V regulator.

 

 

 

 

 

 

 

Revision 1.1 (05-29-08)

18

SMSC USB2250/50i/51/51i

DATASHEET