•Note For Printed Wiring Boards and Schematic Diagrams
Note on Printed Wiring Board:
•X : parts extracted from the component side.
•Y : parts extracted from the conductor side.
•z : Through hole.
•f : internal component.
• : Pattern from the side which enables seeing. (The other layers' patterns are not indicated.)
Caution: |
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Pattern face side: | Parts on the pattern face side seen from |
(Conductor Side) | the pattern face are indicated. |
Parts face side: | Parts on the parts face side seen from |
(Component Side) | the parts face are indicated. |
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Caution: |
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Pattern face side: | Parts on the pattern face side seen from |
(Side B) | the pattern face are indicated. |
Parts face side: | Parts on the parts face side seen from |
(Side A) | the parts face are indicated. |
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* Replacement of IC401, IC501, IC601, IC801 and IC802 used in this set requires a special tool.
•MAIN board is
However, the patterns of
•Lead Layouts
surface
Lead layout of conventional IC | CSP (chip size package) |
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Note on Schematic Diagram:
•All capacitors are in ∝F unless otherwise noted. (p: pF) 50 WV or less are not indicated except for electrolytics and tantalums.
•All resistors are in Ω and 1/4 W or less unless otherwise specified.
•f : internal component.
•C : panel designation.
Note: The components identified by mark 0 or dotted line with mark 0 are critical for safety.
Replace only with part number specified.
•A : B+ Line.
•Power voltage is dc 3.7 V and fed with regulated dc power supply from rechargeable battery terminal.
•Voltages and waveforms are dc with respect to ground under
no mark : PLAYBACK
[ | ] : PLAYBACK (SERVO OFF) |
( | ) : PLAYBACK (SERVO ON) |
∗: Impossible to measure
•Voltages are taken with a VOM (Input impedance 10 MΩ ). Voltage variations may be noted due to normal produc- tion tolerances.
•Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc- tion tolerances.
•Circled numbers refer to waveforms.
•Signal path.
E : PLAYBACK
j : REC
d : USB input from PC
G : USB output to PC
*Replacement of IC401, IC501, IC601, IC801 and IC802 used in this set requires a special tool.
•The voltage and waveform of CSP (chip size package) cannot be measured, because its lead layout is different form that of conventional IC.
•Waveforms
– MAIN Board –
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| IC701 1 | (VI1), 2 (WI1), | 7 IC501 wh (CLK) (Servo on) | ||||||||||||||
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| th | (UI1) (Servo on) |
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| 2.2 |
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| 7.6 ms |
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| 88 ns | |||
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| 1 V/DIV, 5 ms/DIV | 1 V/DIV, 50 ns/DIV | ||||||||||||
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2 IC701 tg (PWM1) (Servo on) | 8 IC901 yd (CLK) | |||||||||||||||
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| 2.5 | 2.7 | ||||
| 11.3 ∝s |
| 5.7 ∝s | ||||
| 1 V/DIV, 5 ∝s/DIV | 1 V/DIV, 5 ∝s/DIV | |||||
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3 IC501 1 (IX) (Servo on) | 9 IC351 wd (MCK) | ||||||
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1.8
190 | 44.3 ns |
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50 mV/DIV, 200 ns/DIV | 1 V/DIV, 20 ns/DIV |
4 IC501 8 (RFO) (Servo on) | q; IC871 8 (OSCOUT) |
1.2 | 1 |
∝ | |
| 30.5 s |
500 mV/DIV, 100 ns/DIV | 500 mV/DIV, 10 ∝s/DIV |
5 IC501 ra (FE) (Servo on) | qa IC801 <czz (OSCO) |
Approx. |
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| 2.7 |
60 |
| 44.3 ns |
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20 mV/DIV, 1 ∝s/DIV | 1 V/DIV, 20 ns/DIV |
6IC501 rs (TE) (Servo on)
Approx. 350
100 mV/DIV, 1 ∝s/DIV
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