Pin No. |
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69 |
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| UNISO | O |
| Serial data output terminal for the unilink | Not used (open) | ||||||||||||||||
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70 |
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| UNISI | I |
| Serial data input terminal for the unilink | Not used (fixed at “L”) | ||||||||||||||||
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71 |
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| UNICKO | O |
| Serial data transfer clock signal output terminal for the unilink Not used (connected to pin ^¥) | |||||||||||||||||
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72 |
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| BUSON | O |
| Bus on/off control signal output terminal | Not used (pull up) | ||||||||||||||||
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73 |
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| SYSRST | O |
| Reset signal output terminal | “L”: reset | Not used (pull up) | |||||||||||||||
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74 |
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| VREG | O |
| CPU regulator output terminal |
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| Connected to capacitor | ||||||||||||||
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75 |
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| GND | — |
| Ground terminal |
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76 |
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| X OUT | O |
| Main system clock output terminal (4.5 MHz) | |||||||||||||||||
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77 |
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| X IN | I |
| Main system clock input terminal (4.5 MHz) | |||||||||||||||||
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78 |
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| CE | I |
| CPU chip enable signal input (fixed at “H”) | |||||||||||||||||
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79 |
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| VDD1 | — |
| Power supply terminal (+5V) |
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80 |
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| RESET | I |
| System reset signal input from the reset signal generator (IC551) and reset switch (S551) | |||||||||||||||||
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| “L” is input for several 100 msec after power on, then it changes to “H” | ||||||||||||||||||||
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*1 loading/tape operation motor control |
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| MODE |
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| STOP |
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| LOADING/ |
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| EJECT/ |
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| BRAKE |
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TERMINAL |
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| FORWARD |
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| REVERSE |
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| LM LOD (pin 8) |
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| “L” |
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| “H” |
| “L” |
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| “H” |
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| LM EJ (pin 9) |
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| “L” |
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| “L” |
| “H” |
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| “H” |
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– 19 –