Sun Microsystems 240 manual UltraSPARC IIIi Processor, Cpu

P8 Netra 240 Server Architecture Sun Microsystems, Inc.

•Two USB ports

•One full-length PCI slots and two half-length PCI slots

•Daughter-board connector for the optional Sun Crypto Accelerator 500 board

•System management controller service processor for remote management (ALOM)

Figure 2-3 is a block-level diagram of the motherboard in the Netra 240 server and illustrates the components that provide key functionality. The following sections discuss these key components.

ALOM

System

Serial

DIMMs

DIMMs

Management

Controller

ALOM

Network

UltraSPARC IIIi

UltraSPARC IIIi

CPU

CPU

SCA 500

J-Bus (128-bit, 152-160 MHz)

South Bridge

DVD-ROM

PCI2a

Interrupt

(General I/O)

JIO

JIO

Ultra160

Hostbridge

Hostbridge

PCI1a

SCSI

PCI slot

PCI2b

PCI1b

64-bit, 33MHz

Dual

PCI slot

Dual

Disk 0

Gigabit

64-bit,

Gigabit

Ethernet

33/66 MHz

Ethernet

Disk 1

Serial

PCI slot

64-bit, 33MHz

USB0

USB1

Ethernet 0

Ethernet 1

Ethernet 2

Ethernet 3

SCSI

Power

Power

Supply

Supply

Unit 0

Unit 1

Figure 2-3: Block diagram of the Netra 240 motherboard.

UltraSPARC IIIi Processor

Based on Sun’s flagship UltraSPARC III processor, the UltraSPARC IIIi processor in the Netra 240 server combines high performance with a full feature set. The highly-integrated UltraSPARC IIIi offers low power consumption, making it ideal for small compact servers and high-density server environments. The UltraSPARC IIIi processor, packaged in a 959-pin ceramic uPGA, is fabricated with a seven-layer 0.13 micron copper process that results in less than 50 watts consumption at 1.28 GHz.

The Netra 240 server’s UltraSPARC IIIi processor runs at 1.28 GHz, incorporating on-chip memory management and bus interfaces to facilitate easy and economical integration of cost-effective systems. The UltraSPARC IIIi processor also provides the following features for smaller multiprocessor systems:

•The 64-bit, 4-way superscalar SPARC V9 pipeline provides high performance in a low-power consumption package.

•The Memory Controller/System Interface unit manages virtual to physical memory address mappings with reduced memory latency and large memory support for up to 4 GB of memory per CPU.

•A 32-KB, 4-way associative instruction cache (I-cache) and a 64-KB, 4-way associative data cache (D-cache) help ensure low-latency access to instructions and data.

•A 1-MB, 4-way associative on-chip L2 cache running at half the CPU core frequency provides increased reliability and high throughput that scales with processor technology improvements.

•The 128-bit (152 MHz or 160 MHz) J-Bus system interface provides a simple, lightweight system interconnect optimized for small multiprocessor systems.