Integral address decoder - provides selection of all primary and
secondary ISA addresses including COM1-4 and LPT1-3.
Enhanced Power Management Fun ction
Special configuration registers for power down
Enhanced programmable power-down and wake-up modes
Auto power-down and wake-up modes
3 special pins for power management
Typical current consumption during power-down is less than 10A
4.2.3 Video Subsystem
The video subsystem, implemented on the Main Board and on the LCD
Display Unit, displays text, graphics and drives an external VGA port. The
video subsystem is implemented with a Chips and Technology hig h
performance flat panel/RT VGA controller and supporting logic and video
RAM (1 MB).
The major features of the VGA controller include:
Highly integrated design (flat panel / CRT VGA controller, RAMDAC,
clock synthesizer)
Multiple Bus Architecture Integrated Interface
Local Bus (32-bit CPU Direct and VL)
PCI Bus
EISA/ISA (PC/AT) 16-bit Bus
Advanced frame buffer architecture uses available display memory,
maximizing integration and minimizing chip count
Integrated programmable linear address feature accelerates GUI
performance
High performance resulting from zero wait state writes (write buffer) and
minimum wait state reads (internal asynchronous FIFO design)
Supports panel resolutions up to 800 x 600
SMARTMAP intelligent color to gray scale conversion enhances text
legibility
Text enhancement feature improves white text contrast on flat panel
displays
Fully Compatible with IBM VGA
4-4 Theory of Operation