Texas Instruments TI SITARA manual CORTEX A-8 Highlights, First ARMv7 instruction-set architecture

CORTEX A-8 : Highlights

•First ARMv7 instruction-set architecture

•Superscalar architecture delivers high performance

–Advanced dynamic Branch prediction

•256 KB unified L2 cache

–Dedicated, low-latency, high-BW interface to L1 cache

•Enhanced VFPv3

–Doubles number of double-precision registers

–Adds new instructions to convert between fixed and floating point ting point

•Efficient Run Time Compilation Target

–Jazelle-RCT: Target for Java. Memory footprint reduced up to 3x

•Trust Zone

–Normal & Secure worlds have different memory views

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