Texas Instruments TI SITARA PRU operation is little endian, Includes Interrupt Controller for

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PRU Subsystem

Provides two independent

programmable real-time (PRU)PRU Subsystem Functional Block Diagram

cores

• 32-Bit Load/Store RISC		32 GPO
architecture		30 GPI
• 4K Byte instruction RAM (1K
instructions) per core		32 GPO
• 512 Bytes data RAM per core
		30 GPI
PRU operation is little endian
Includes Interrupt Controller for
system event handling		Interrupts to
I/O interface
		ARM INTC
• 30 input pins and 32 output
	Peripherals +
		Events from
pins per PRU core (AM18x)		PRUs

•AM17x does not support PRU I/O

Power management via single power/sleep controller (PSC)

PRU0 Core

4KB IRAM

PRU1 Core

4KB IRAM

Interrupt

Controller

(INTC)

32-bit Interconnect SCR

DRAM0

(512 Bytes)

DRAM1

(512 Bytes)

Master I/F (to SCR2)

Slave I/F

(from SCR2)

http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit_Subsystem

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