TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
8

APPLICATION INFORMATION

Figure 9 shows the schematic diagram for a typical
TPS54810 application. The TPS54810 (U1) can provide
up to 8 A of output current at a nominal output voltage of
1.8 V. For proper thermal performance, the PowerPAD
underneath the integrated circuit TPS54810 needs to be
soldered well to the printed-circuit board.
28
6
VIN 24
23
22
21
20
VIN
VIN
VIN
VIN
14
13
12
11
10
9
8
7
PH
PH
PH
PH
PH
PH
PH
PH
PH
5
BOOT
19
18
17
16
15
PGND
PGND
PGND
PGND
PGND
PWRPAD
AGND
VSENSE
COMP
PWRGD
SS/ENA
SYNC
RT
27
26
VBIAS
25
4
3
2
1
U1
TPS54810PWP
0.047 µF
C9
0.047 µF
L1
0.65 µH
C8
22 µF
C10
10 µF
C12
10 µF
VO
3300 pF
VI
R7
2.4 Ω
C11
3300 pF
C7
22 µF
C5
22 µF
R6
71.5 kΩ
C6
1 µF
C3
R5
10 kΩ
C4
R3
10 kΩ
150 pF
C2
R2
301 Ω
1000 pF
C1
R1
10 kΩ
R4
9.76 kΩ
Analog and Power Grounds are Tied at the Pad Under the Package of IC

Figure 9. Application Circuit

COMPONENT SELECTION

The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional design information is available
at www.ti.com.

INPUT FILTER

The input voltage is a nominal 5 VDC. The input filter C10
is a 10-µF ceramic capacitor (Taiyo Yuden). C12, also a
10-µF ceramic capacitor (Taiyo Yuden) provides high
frequency decoupling of the TPS54810 from the input
supply and must be located as close as possible to the
device. Ripple current is carried in both C10 and C12, and
the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, and C8.

FEEDBACK CIRCUIT

The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R1 and R4 sets the output voltage for the circuit
at 1.8 V. R1, along with R2, R3, C1, C2, and C4 forms the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.

OPERATING FREQUENCY

In the application circuit, RT is grounded through a 71.5 kΩ
resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68kΩ to 180 kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default of 350 kHz. The resistance can
be approximated using the following equation:

R+500 kHz

Switching Frequency 100 [kW]

OUTPUT FILTER

The output filter is composed of a 0.65-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Pulse Engineering PA0277. The
capacitors used are 22-µF, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.

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