Transcend Information TS2G-8GCF266 specification

TS2G~8GCF266		266X CompactFlash Card

Pin Replacement Register (Base + 04h in Attribute Memory)





Transcend Information Inc.		37

Image 37

Transcend Information TS2G-8GCF266 manual Pin Replacement Register Base + 04h in Attribute Memory

Contents

Dimensions Placement FeaturesDescription Transcend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Pull-up pin 45 BVD2 to avoid sensing their batteries as Low TS2G~8GCF266266X CompactFlash Card Series termination required for Ultra DMA operation Ultra DMA Electrical RequirementsTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS2G~8GCF266 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS2G~8GCF266 Output Write Timing Specification TS2G~8GCF266 True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing Specification TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Single Function CF+ Cards Card ConfigurationMultiple Function CF+ Cards Table CF+ Card Register and Memory Space Decoding Table CF+ Card Configuration Registers Decoding Attribute Memory Function Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS2G~8GCF266 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O Function Table Common Memory Function Common Memory Transfer Function True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address Configurations Table Contiguous I/O Decoding Contiguous I/O Mapped Addressing Memory Mapped Addressing True IDE Mode Addressing Data Register Address 1F0h170hOffset 0,8,9 CF-ATA Registers Sector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h Offset TS2G~8GCF266 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90h Format Track 50h Flush Cache E7h Identify Device Ech TS2G~8GCF266 Word 0 General Configuration Word 3 Default Number of Heads Word 1 Default Number of CylindersWord 6 Default Number of Sectors per Track Word 49 Capabilities Bit 13 Standby Timer Total Sectors Addressable in LBA Mode Multiple Sector SettingTranslation Parameters Valid Current Number of Cylinders, Heads, Sectors/Track Word 65 Minimum Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedRecommended Multiword DMA transfer cycle time Word 68 Minimum PIO transfer cycle time with Iordy Words 85-87 Features/command sets enabled Word 89 Time required for Security erase unit completion Word 88 Ultra DMA Modes Supported and Selected Word 160 Power Requirement Description Word 91 Advanced power management level valueWord 128 Security Status Bit 8 Security Level Additional Requirements for CF Advanced Timing Modes TS2G~8GCF266 Idle 97h or E3h Initialize Drive Parameters 91h Idle Immediate 95h or E1hNOP 00h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4h TS2G~8GCF266 Recalibrate 1Xh Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS2G~8GCF266 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87h Wear Level F5h Write Buffer E8h Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 Error Posting Smart Command Set Smart Feature Register Values Smart Command SetS. Table Capacity Decription Smart Data Structure