CF-ATA Registers | Transcend Information TS2G-8GCF266 specification

TS2G~8GCF266		266X CompactFlash Card

CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the “task file.”

Data Register (Address - 1F0h[170h];Offset 0,8,9)

The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register.

Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)

This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register.

This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low and -CE1 high.

Bit 7 (BBK/ICRC): this bit is set when a Bad Block is detected. This bit is also set when an interface CRC error is detected in True IDE Ultra DMA modes of operation.

Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.

Bit 5: this bit is 0.

Bit 4 (IDNF): the requested sector ID is in error or cannot be found.

Bit 3: this bit is 0.

Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued.

Bit 1 This bit is 0.

Bit 0 (AMNF) This bit is set in case of a general error.

Transcend Information Inc.

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Image 47

Transcend Information TS2G-8GCF266 manual CF-ATA Registers, Data Register Address 1F0h170hOffset 0,8,9

Contents

Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Pull-up pin 45 BVD2 to avoid sensing their batteries as Low TS2G~8GCF266266X CompactFlash Card Table Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS2G~8GCF266 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS2G~8GCF266 Output Write Timing Specification TS2G~8GCF266 True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing Specification TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Multiple Function CF+ Cards Card ConfigurationSingle Function CF+ Cards Table CF+ Card Register and Memory Space Decoding Table CF+ Card Configuration Registers Decoding Attribute Memory Function Attribute Memory Function Configuration Option Register Base + 00h in Attribute Memory TS2G~8GCF266 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O Function Table Common Memory Function Common Memory Transfer Function True IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address Configurations Table Contiguous I/O Decoding Contiguous I/O Mapped Addressing Memory Mapped Addressing True IDE Mode Addressing Data Register Address 1F0h170hOffset 0,8,9 CF-ATA Registers Cylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h Offset TS2G~8GCF266 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90h Format Track 50h Flush Cache E7h Identify Device Ech TS2G~8GCF266 Word 0 General Configuration Word 49 Capabilities Bit 13 Standby Timer Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 6 Default Number of Sectors per Track Current Number of Cylinders, Heads, Sectors/Track Multiple Sector SettingTotal Sectors Addressable in LBA Mode Translation Parameters Valid Word 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 65 Minimum Multiword DMA transfer cycle time Recommended Multiword DMA transfer cycle time Words 85-87 Features/command sets enabled Word 89 Time required for Security erase unit completion Word 88 Ultra DMA Modes Supported and Selected Additional Requirements for CF Advanced Timing Modes Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 128 Security Status Bit 8 Security Level TS2G~8GCF266 Idle 97h or E3h NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4h TS2G~8GCF266 Recalibrate 1Xh Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS2G~8GCF266 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87h Wear Level F5h Write Buffer E8h Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 Error Posting S. Table Capacity Smart Command SetSmart Command Set Smart Feature Register Values Decription Smart Data Structure