MDS-JE770
• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Pin No. | Pin Name | I/O |
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1 | MNT0 (FOK) | O |
| Not used (open) | |||
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2 | MNT1 (SHCK) | O |
| Track jump detection signal output to the system control | |||
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3 | MNT2 (XBUSY) | O |
| In the state of executire command signal output | |||
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4 | MNT3 (SLOC) | O |
| Not used (open) | |||
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5 | SWDT | I |
| Writing data signal input from the system control | |||
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6 | SCLK | I (S) |
| Serial clock signal input from the system control | |||
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7 | XLAT | I (S) |
| Serial latch signal input from the system control | |||
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8 | SRDT | O (3) |
| Reading data signal output to the system control | |||
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9 | SENS | O (3) |
| Internal status (SENSE) output to the system control | |||
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10 | XRST | I (S) |
| Reset signal input from the system control “L”: Reset | |||
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11 | SQSY | O |
| Subcode Q sync (SCOR) output to the system control | |||
| “L” is output every 13.3 msec. Almost all, “H” is output | ||||||
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12 | DQSY | O |
| Digital In | |||
| control | ||||||
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13 | RECP | I |
| Laser power switching input from the system control “H”: Recording, “L”: Playback | |||
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14 | XINT | O |
| Interrupt status output to the system control | |||
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15 | TX | O |
| Recording data output enable input from the system control | |||
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16 | OSCI | I |
| System clock input (512Fs=22.5792 MHz) | |||
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17 | OSCO | O |
| System clock output (512Fs=22.5792 MHz) (Not used) | |||
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18 | XTSL | I |
| System clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”) | |||
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19 | DIN0 | I |
| Digital audio input (Optical input) | |||
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20 | DIN1 | I |
| Digital audio input (Optical input) (Not used) | |||
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21 | DOUT | O |
| Digital audio output (Optical output) (Not used) | |||
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22 | DADTI | I |
| Serial data input | |||
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23 | LRCKI | I |
| LR clock input “H” : Lch, “L” : R ch | |||
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24 | XBCKI | I |
| Serial data clock input | |||
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25 | ADDT | I |
| Data input from the A/D converter | |||
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26 | DADT | O |
| Data output to the D/A converter | |||
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27 | LRCK | — |
| LR clock output for the A/D and D/A converter (44.1 kHz) | |||
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28 | XBCK | O |
| Bit clock output to the A/D and D/A converter (2.8224 MHz) | |||
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29 | FS256 | O |
| 11.2896 MHz clock output (Not used) | |||
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30 | DVDD | I |
| +3V power supply (Digital) | |||
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31 - 34 | A03 to A00 | O |
| DRAM address output | |||
35 | A10 | O |
| DRAM address output (Not used) | |||
36 - 40 | A04 to A08 | O |
| DRAM address output | |||
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41 | A11 | O |
| DRAM address output (Not used) | |||
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42 | DVSS | — |
| Ground (Digital) | |||
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43 | XOE | O |
| Output enable output for DRAM | |||
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44 | XCAS | O |
| CAS signal output for DRAM | |||
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45 | A09 | O |
| Address output for DRAM | |||
46 | XRAS | O |
| RAS signal output for DRAM | |||
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47 | XWE | O |
| Write enable signal output for DRAM | |||
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* I (S) stands for Schmidt input, I (A) for analog input, O (3) for
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