Intel MPCBL0010 manual Maintenance, Supervision, Diagnostics, In-Target Probe ITP

Page 178

Maintenance—MPCBL0010 SBC

13.0Maintenance

13.1Supervision

Table 151 lists the main components that perform hardware monitoring of voltages and timers.

Table 151. Hardware Monitoring Components

Component

Function

Monitors

 

 

 

Intelligent Platform Management

 

Commands from the BIOS. If the timer expires (times out),

WDT #1

causes a hard reset, power down, or power cycle and IPMI

Controller (IPMC)

 

event.

 

 

 

 

 

6300ESB (Intel® 82801CA I/O

WDT #3

The first attempt to fetch an instruction after a power

Controller Hub 3)

failure.

 

 

 

 

 

 

Strobed by IPMC firmware. If it expires, it isolates The

FWUM (R1C13)

WDT #2

MPCBL0010 SBC from the backplane IPMB buses, and

resets the IPMC. Also performs fail safe field upgrade of the

 

 

 

 

IPMC.

 

 

 

13.2Diagnostics

13.2.1In-Target Probe (ITP)

The ITP connector supports the use of a tool that helps you observe and control the step-by-step execution of your program for debugging hardware and software. Debugging includes finding a hardware or software error and identifying the location and cause of the error so it can be corrected.

To maximize the development and delivery of mission-critical tools, we works with third party vendors to develop and deliver specific tools. The following vendors provide in- circuit emulation hardware and software:

•American Arium* currently develops in-circuit emulation and run control tools for Intel processors.

http://www.arium.com/

•Agilent Technologies* currently develops logic analyzer and probing tools for Intel processors.

http://we.home.agilent.com

•Tektronix* currently develops logic analyzer and probing tools for Intel processors. http://www.tek.com/Measurement/logic_analyzers/index.html

 

Intel NetStructure® MPCBL0010 Single Board Computer

October 2006

Technical Product Specification

Order Number: 304120

177

Page 177 Page 179
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Contents Technical Product Specification Intel NetStructure MPCBL0010 Single Board ComputerOrder Number Contents 1.2 Weight1.1 1.3PwrBtn usage 10.8 OEM Ipmi Commands10.8.1 Reset Bios Flash Type Hardware Management Overview10.8.2.1 10.8.2131 132177 Component Technology 179 Warranty Information 180 16.1178 AdvancedMC Direct Connect Switch Block Diagram Safety Warnings20.5 Chinese Safety Warning Warm Reset Block DiagramSupported Memory Configurations Jumper Definitions Tables102 100101 103Reset Actions 140 Reset Bios Flash Type 131Hot Swap LED Signals 136 SOL Configuration Reference Script Command-line Options 151Revision History Date Revision DescriptionIntroduction Document OrganizationGlossary See the Low Pin Count LPC Interface specification That allows your networked client computer to boot using aIntelligent Platform Management Bus. Physical two-wire Phase-locked LoopApplication Feature OverviewFunctional Description Low Voltage Intel Xeon Processor Chipset2.2 I/O Controller Hub Memory J10, J12Memory Controller Hub 2.3 64-Bit PCI Hub4 I/O TimersSupported Memory Configurations 4.1 I/O Controller Hub4.5 10/100 Fast Ethernet AdvancedMC AMC Connector J18, J19Gigabit Ethernet 4.6 USB6.1 FWH0 Main Bios Firmware HubsFlash ROM Backup Mechanism Onboard Power Supplies6.2 FWH1 Backup/Recovery Bios Power Feed FusesIpmc Telecom ClockAdvancedMC Direct Connect AdvancedMCA Direct Connect Switch Block Diagram AdvancedTCA ComplianceOperating the Unit JumpersName Function with Jumper Present On Removed Off MPCBL0010 SBCAdvancedMC Filler Panels AdvancedMC Filler PanelInstalling Memory Remove the coverInstalling and Extracting the SBC Insert two matched pair DIMMsChassis Installation Chassis ExtractionSolid blue Remote Access Configuration AdvancedMC Module Installation and ExtractionBios Configuration Software UpdatesLoading\Saving Custom Bios Configuration Bios UpdatesBios Image Command Behavior Copying BIOS.bin from the SBC Saving BIOS.bin to the SBCIpmc Firmware Upgrade Using the KCS Interface Ipmc Firmware UpdatesFlashlnx Command Line Options Flashlnx Utility Command Line OptionsDigital Ground and Chassis Ground Isolated Default Digital Ground to Chassis Ground ConnectivityEnvironmental Specifications SpecificationsMechanical Specifications Board OutlineEnvironmental Assumptions Reliability SpecificationsMean Time Between Failure Mtbf Specifications General AssumptionsPower Consumption WeightPower Requirements General NotesConnectors and LEDs Connectors and LEDs-MPCBL0010 SBC Backplane Description ConnectorsFront Panel Front Panel Connector Assignments Front Panel Description ConnectorsBackplane Connectors Power Distribution Connector P10Power Distribution Connector Zone 1 P10 Pin Assignments AdvancedTCA Data Transport Connector J23Pin Signal Description Data Transport Connector Zone 2 J23 Alignment Blocks AdvancedTCA Data Transport Connector J20AdvancedTCA* Data Transport Connector Zone 2 J20 Pin PinExtended IPT700 Debug Port Connector J25 On-Board ConnectorsPost Code Connector J13 Post Code Connector Pin AssignmentsEthernet 10/100 Debug Connector LED Operation Front Panel ConnectorsEthernet 10/100 Debug Connector J3 FunctionUSB Connector J4 Serial Port Connector J5AdvancedMC* Connectors J18, J19 Serial Port Connector J5 Pin AssignmentsAdvancedMC* Connector Pin Assignments AdvancedMC* Connector LEDsOOS Front Panel LED Descriptions Sheet 1 OOSPost LED Codes Front Panel LED Descriptions Sheet 2Reset Button Example Post LED CodesRedundant Bios Functionality Bios FeaturesBios Flash Memory Organization IntroductionLegacy USB Support Recovering Bios DataBoot Options Language SupportCD-ROM and Network Boot Fast Booting SystemsBios Security Features Booting without Attached DevicesKey Escape Sequence Supervisor and User Password FunctionsFunction Key Escape Code Equivalents Sheet 1 ESC OP ESC OQ ESC or ESC OSESC OY Function Key Escape Code Equivalents Sheet 2ESC OW ESC OX ESC OZBios Setup Program Function Keys Bios SetupBios Setup Program Menu Bar Main MenuAdvanced Menu Feature Options DescriptionBios ID Main MenuAdvanced Menu CPU Configuration Sub-MenuPicmg Shows the sub-menu options for configuring the CPU IDE Configuration Sub-MenuCPU Configuration Sub-Menu Shows the IDE configuration options IDE Configuration Sub-MenuShows the IDE Master/Slave configuration options Primary IDE Master/Slave Configuration OptionsIDE Master/Slave Sub-Menu SuperIO Configuration Sub-Menu Shows SuperIO configuration optionsAcpi Configuration Sub-Menu SuperIO Configuration Sub-MenuShows Acpi configuration options Advanced Acpi Configuration Sub-MenuChipset Acpi Configuration Sub-Menu Acpi Configuration Sub-MenuShows the System Management information Chipset Acpi Configuration Sub-MenuSystem Management Sub-Menu Apic Acpi SCI IRQShows event log configuration options Event Log Configuration Sub-MenuSystem Management Sub-Menu Event Log Configuration Sub-Menu PCI Express Error Masking Configuration Sub-MenuPCI Express Error Masking Configuration Sub-Menu MPS Configuration Sub-Menu MPS Configuration Sub-MenuShows MPS Configuration options AdvancedTCA* Channel Routing PICMG* Sub-MenuOn-board Devices Configuration Sub-Menu AdvancedTCA Channel Routing Picmg Sub-MenuOn-board Devices Configuration Sub-Menu PCI Express* Configuration Sub-MenuShows On-board Devices Configuration options Option ROM Configuration OptionsShows PCI Express configuration options Remote Access Configuration Sub-MenuPCI Express* Configuration Sub-Menu Shows remote access configuration options Ipmi Configuration Sub-MenuRemote Access Configuration Sub-Menu Shows the LAN configuration options Shows the Ipmi configuration optionsIpmi Configuration Sub-Menu LAN Configuration Sub-MenuShows USB configuration options USB Configuration Sub-MenuUSB Configuration Sub-Menu PCIPnP Menu USB Mass Storage Device ConfigurationUSB Mass Storage Device Configuration PCIPnP MenuBoot Menu Boot MenuBoot Settings Configuration Sub-Menu Shows Boot Settings Configuration optionsShows Boot Device Priority options Boot Device Priority Sub-MenuBoot Settings Configuration Sub-Menu Sheet 2 Boot Device Priority Sub-MenuHard Disk Drives Sub-menu OS Load Timeout Timer Sub-MenuShows OS Load Timeout Timer options Shows Hard Disk Drives optionsSecurity Menu OS Load Timeout Timer Sub-MenuShows passwords and security features Chipset MenuNorthbridge Chipset Configuration Northbridge Configuration Sub-MenuDescribes the sub-menus used to select chipset features Chipset MenuExit Menu Spread Spectrum Clocking Mode Sub-MenuSpread Spectrum Clocking Mode Configuration Exit MenuExit Menu Bios Error Messages Error MessagesBios Error Messages Cmos Checksum BAD Clear Cmos Jumper enabledCheckpoint Description Bootblock Initialization Code CheckpointsPost Code Checkpoints SmramEarly CPU Init Exit DIM Code Checkpoints Acpi Runtime CheckpointsAddressing PCI Configuration MapPCI Configuration Map Lists the PCI devices and the bus on which they resideAMC B2 AMC B1 Fpga Registers Symbol DescriptionFpga Register Legend Post Codes 0080h Fpga Register OverviewExtended Post Codes 0081h Debug LED 0A01h Fpga Version 0A00hVersion Programmable logic version Address ActionFwum Ready Fwum Busy Development Features 0A04hFwum 0A02h PCB PCB versionTelecom Clock Register 0 0A08h Hwmode Holos MS2 MS1 Refalign FCS E3DS3Telecom Clock Register 1 0A09h Telecom Clock Register 2 0A0AhTelecom Clock Register 4 0A0Ch Telecom Clock Register 3 0A0BhTransmission Frequency Selection TXREFxSEL2..0 Transmission Clock FrequencyTelecom Clock Register 6 0A0Eh 0xA0D Write ResetUnlock Hldovr SEC10 SEC01 PRI10 PRI01 Ipmc Register Legend Ipmc AddressesTelecom Clock Register 7 0A0Fh Address FunctionLtype Ltest Uart Brst SBC Control 00hHT0 PwrBtn usage Post Code High 03h SBC Status 01hPost Code Low 02h LED Color Control 06hAdvancedMC B1 Control & Status 10h AdvancedMC B1 Control & Status 11hAMC B2 Control & Status 12h AdvancedMC B2 Control & Status 13hVID5 VID4 VID3 VID2 VID1 VID0 CPU 0 VIDs 18hADC Grab Control 20h Mcerr HOT Trip VTT IerrFabric Control 1 24h ADC1 and ADC2 Grab Data 21-22hPCB 3VOC Reset Events 29h Reset Source 27hDefault configuration connects FWH0 and FWH1 to the ICH Fabric Control 2 25hCrosspoint Switch Control 2Ah Miscellaneous Controls and Status 2Dh Crosspoint Switch Ports RegisterCrosspoint Switch Data 2Bh Ipmc Post Codes FEhAddress Action FFh Read Reserved Version Write PowerUp Version FFhHardware Management Overview Intelligent Platform Management Controller IpmcIpmc Block Diagram Green to Red Sensor Data Record SDRHardware Sensors Sheet 1 State M1Hardware Sensors Sheet 2 Hardware Sensors Sheet 3 OEM Sensor Types Hardware Sensors Sheet 4OEM Name OEM Number Description SEL Events Supported Sheet 1 System Event Log SELOEM Event/Reading Type Sensor Sensor Type Specific Event Description CodePCI Perr SEL Events Supported Sheet 2PCI Serr SO/GOSEL Events Supported Sheet 3 When name is FIA FRU Initialization SEL Events Supported Sheet 4Sensor Sensor Type Specific Event Description Code Offset SEL Events Supported Sheet 5OEM Variable Size Data Type Bytes Ipmb Link SensorField Replaceable Unit FRU Information ASC-IILinuxCustFru Utility Usage Customizable FRU AreaFRU Customer Area Example 1. Input File SeecommonAB AC AD AE AF OEM Ipmi Commands KeyingBoard Device Channel Port Selection Identifiers Reset Bios Flash TypeReset Bios Flash Type Channel Port Selection IdentifiersSetBoardDeviceChannelPortSelection SetBoardDeviceChannelPortSelectionResponse GetBoardDeviceChannelPortSelection GetBoardDeviceChannelPortSelectionGetBoardDevicePossibleSelection GetBoardDevicePossibleSelectionControls Identifier Table Set Control StateGet Control State Set Control StateControl Description Control Number Hot Swap ProcessControls Identifier FWHHot Swap LED Hot Swap LED SignalsAdvancedMC Module Activation LED Status MeaningTemperature and Voltage Sensors Pre-Defined Resources for AdvancedMC ModulesSensors and Thresholds Version SDR Processor Events System Firmware Progress Post ErrorSystem Acpi Power State Dimm Memory EventsReset Action System Function Memory Status ResetReset Actions Ipmb Link SensorWarm Reset Hard ResetIpmc Firmware Code Ipmc Firmware Code Process MPCBL0010 SBC-Hardware Management Overview SOL Architecture Serial Over LAN SOLReferences SOL ImplementationSOL Block Diagram Front Panel Serial Port or Rear Transition Module Theory of OperationArchitectural Components Serial Over LANReference Configuration Script Serial Over LAN ClientConfiguring the Blade for SOL Supported Usage ModelReference Script referencecfg SOL Configuration Reference Script referencecfgDefault Behavior SOL User InformationSOL Parameters Command Line OptionsSOL Configuration Reference Script Command-line Options Channel ParametersTarget Blade Setup Setting up a Serial Over LAN SessionBios Configuration Operating System Configuration Change the serial parameter to readChange the kernel line to read For RhelSbcutils RPM Installation Execute the referencecfg ScriptExecute this command to configure SOL on the target blade Script executed on the Intel CMMExecute this command to restart the network Client Blade SetupConfigure the Ethernet Port For RedHat* Rhel Configure IP address of the Ethernet portChecking SOL Configuration Installing ipmitoolStart an SOL Session Ending an SOL Session OEMOperating Systems for SOL Client ipmitool Block Diagram of the Telecom Clock Telecom ClockInterface Description Function DescriptionAlarm Handling Recovered Clock SelectionConfiguration Operational ConfigurationModule Transmission Frequency Selection Enable/Disable Transmission ClockTelecom Clock API Name Used For ValueAutomatic Switchover Mode Recovered ClockAutomatic Switchover Automatic Switchover ValuesReference Frequency for PLL Select Reference ClockPrimary/Secondary Redundant Clock Corner Frequency PLL Operating ModeHardware Reset Reference Clock AlignmentAlarm State Values Read Alarm StatesHardware Reset Values Read New EventsReference Clock Values Read the Current Reference ClockSysfs Interface Telecom Clock API Function Mapping for the sysfs Interface80h Telecom Clock RegistersA10-A1Fh October Technical Product Specification Order Number 171 DRVCLKB1 DRVCLKA1 DRVCLKB0 DRVCLKA0 Addres Action UNLOCK10 UNLOCK01 HLDOVR10 HLDOVR01 SEC10 SEC01 PRI10 PRI01 October Technical Product Specification Order Number 175 FPGA/PLD Serial Link Bit Definition Bit Write ReadSupervision MaintenanceDiagnostics In-Target Probe ITPPower vs. Flow Rate ThermalsComponent Technology Returning a Defective Product RMA Warranty InformationFor the Americas For Asia and Pacific Apac For Europe, Middle East, and Africa EmeaLimitation of Liability and Remedies MPCBL0010 SBC-Warranty Information Customer Support Technical Support and Return for Service AssistanceCustomer Support Sales AssistanceCertifications Vcci CisprzzNorth America FCC Class B Agency Information-Class BJapan Vcci Class B Korean Class B Australia, New Zealand Safety Warnings Mesures de Sécurité Sicherheitshinweise Norme di Sicurezza Instrucciones de Seguridad Chinese Safety Warning Appendix a Reference Documents MPCBL0010 SBC-Reference Documents Appendix B List of Supported Commands Ipmi v1.5 and Picmg Ipmi 1.5 Supported Commands Sheet 1Ipmi 1.5 Supported Commands Sheet 2 FRU Device Commands NetFnPicmg 3.0 Ipmi Supported Commands Command NetFn Interface
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