Intel MPCBL0010 manual Primary IDE Master/Slave Configuration Options, IDE Master/Slave Sub-Menu

Page 68

BIOS Setup—MPCBL0010 SBC

Table 30.

IDE Configuration Sub-Menu (Continued)

 

 

 

 

 

Feature

Options

Description

 

 

 

 

 

Hard Disk Write Protect

Disabled

Enable/Disable Hard Disk device write protection. This is

 

Enabled

effective only if the device is accessed through BIOS.

 

 

 

 

 

 

 

 

0

 

 

 

5

 

 

 

10

 

 

IDE Detect Time Out

15

Select the time out value for detecting ATA/ATAPI device(s).

 

20

 

 

 

 

 

25

 

 

 

30

 

 

 

35

 

 

 

 

 

Note: Bold text indicates default setting.

7.3.2.1Primary IDE Master/Slave Configuration Options

Table 31 shows the IDE Master/Slave configuration options.

Table 31.

IDE Master/Slave Sub-Menu

 

 

 

 

 

 

Feature

Options

Description

 

 

 

 

 

Device

 

Display IDE device.

 

 

 

 

 

Vendor

 

Display IDE vendor name.

 

 

 

 

 

Size

 

Display IDE device size.

 

 

 

 

 

LBA Mode

 

Display IDE LBA Mode status.

 

 

 

 

 

Block Mode

 

Display IDE Block Mode status.

 

 

 

 

 

PIO Mode

 

Display PIO Mode status.

 

 

 

 

 

Async DMA

 

Display Async DMA status.

 

 

 

 

 

Ultra DMA

 

Display Ultra DMA-5 status.

 

 

 

 

 

S.M.A.R.T

 

Display S.M.A.R.T status.

 

 

 

 

 

 

Not installed

 

 

Type

Auto

Select the type of IDE device connected.

 

CDROM

 

 

 

 

 

ARMD

 

 

 

 

 

 

 

Disabled

Disable: Disable LBA ModeAuto: Enable the LBA Mode if the

 

LBA/Large Mode

device supports it and the devices is not already formatted with

 

Auto

 

 

LBA Mode disable.

 

 

 

 

 

 

 

 

 

Disabled

Disable: The data transfer from and to the device occurs one

 

Block (Multi-Sector

sector at a time. Auto: The data transfer from and to the

 

Transfer)

Auto

device occurs multiple sectors at a time if the device supports

 

 

 

it.

 

 

 

 

 

PIO Mode

Auto

Select PIO Mode.

 

0/1/2/3/4

 

 

 

 

 

 

 

 

Intel NetStructure® MPCBL0010 Single Board Computer

October 2006

Technical Product Specification

Order Number: 304120

67

Image 68
Contents Technical Product Specification Intel NetStructure MPCBL0010 Single Board ComputerOrder Number Contents Weight 1.11.2 1.310.8 OEM Ipmi Commands 10.8.1 Reset Bios Flash TypePwrBtn usage Hardware Management Overview10.8.2 13110.8.2.1 132178 Component Technology 179 Warranty Information 180 16.1177 Safety Warnings 20.5 Chinese Safety WarningAdvancedMC Direct Connect Switch Block Diagram Warm Reset Block DiagramSupported Memory Configurations Jumper Definitions Tables100 101102 103Reset Bios Flash Type 131 Hot Swap LED Signals 136Reset Actions 140 SOL Configuration Reference Script Command-line Options 151Revision History Date Revision DescriptionIntroduction Document OrganizationGlossary That allows your networked client computer to boot using a Intelligent Platform Management Bus. Physical two-wireSee the Low Pin Count LPC Interface specification Phase-locked LoopFunctional Description Feature OverviewApplication Low Voltage Intel Xeon Processor ChipsetMemory J10, J12 Memory Controller Hub2.2 I/O Controller Hub 2.3 64-Bit PCI HubTimers Supported Memory Configurations4 I/O 4.1 I/O Controller HubAdvancedMC AMC Connector J18, J19 Gigabit Ethernet4.5 10/100 Fast Ethernet 4.6 USB6.1 FWH0 Main Bios Firmware HubsOnboard Power Supplies 6.2 FWH1 Backup/Recovery BiosFlash ROM Backup Mechanism Power Feed FusesIpmc Telecom ClockAdvancedMC Direct Connect AdvancedMCA Direct Connect Switch Block Diagram AdvancedTCA ComplianceOperating the Unit JumpersName Function with Jumper Present On Removed Off MPCBL0010 SBCAdvancedMC Filler Panels AdvancedMC Filler PanelInstalling Memory Remove the coverInstalling and Extracting the SBC Insert two matched pair DIMMsChassis Installation Chassis ExtractionSolid blue AdvancedMC Module Installation and Extraction Bios ConfigurationRemote Access Configuration Software UpdatesBios Image Command Behavior Bios UpdatesLoading\Saving Custom Bios Configuration Copying BIOS.bin from the SBC Saving BIOS.bin to the SBCIpmc Firmware Updates Flashlnx Command Line OptionsIpmc Firmware Upgrade Using the KCS Interface Flashlnx Utility Command Line OptionsDigital Ground and Chassis Ground Isolated Default Digital Ground to Chassis Ground ConnectivitySpecifications Mechanical SpecificationsEnvironmental Specifications Board OutlineReliability Specifications Mean Time Between Failure Mtbf SpecificationsEnvironmental Assumptions General AssumptionsWeight Power RequirementsPower Consumption General NotesConnectors and LEDs Connectors and LEDs-MPCBL0010 SBC Backplane Description ConnectorsFront Panel Front Panel Connector Assignments Front Panel Description ConnectorsBackplane Connectors Power Distribution Connector P10Pin Signal Description AdvancedTCA Data Transport Connector J23Power Distribution Connector Zone 1 P10 Pin Assignments Data Transport Connector Zone 2 J23 AdvancedTCA Data Transport Connector J20 AdvancedTCA* Data Transport Connector Zone 2 J20 PinAlignment Blocks PinOn-Board Connectors Post Code Connector J13Extended IPT700 Debug Port Connector J25 Post Code Connector Pin AssignmentsFront Panel Connectors Ethernet 10/100 Debug Connector J3Ethernet 10/100 Debug Connector LED Operation FunctionUSB Connector J4 Serial Port Connector J5AdvancedMC* Connectors J18, J19 Serial Port Connector J5 Pin AssignmentsAdvancedMC* Connector Pin Assignments AdvancedMC* Connector LEDsOOS Front Panel LED Descriptions Sheet 1 OOSPost LED Codes Front Panel LED Descriptions Sheet 2Reset Button Example Post LED CodesBios Features Bios Flash Memory OrganizationRedundant Bios Functionality IntroductionRecovering Bios Data Boot OptionsLegacy USB Support Language SupportFast Booting Systems Bios Security FeaturesCD-ROM and Network Boot Booting without Attached DevicesSupervisor and User Password Functions Function Key Escape Code Equivalents Sheet 1Key Escape Sequence ESC OP ESC OQ ESC or ESC OSFunction Key Escape Code Equivalents Sheet 2 ESC OW ESC OXESC OY ESC OZBios Setup Bios Setup Program Menu BarBios Setup Program Function Keys Main MenuFeature Options Description Bios IDAdvanced Menu Main MenuPicmg CPU Configuration Sub-MenuAdvanced Menu CPU Configuration Sub-Menu IDE Configuration Sub-MenuShows the sub-menu options for configuring the CPU Shows the IDE configuration options IDE Configuration Sub-MenuIDE Master/Slave Sub-Menu Primary IDE Master/Slave Configuration OptionsShows the IDE Master/Slave configuration options SuperIO Configuration Sub-Menu Shows SuperIO configuration optionsAcpi Configuration Sub-Menu SuperIO Configuration Sub-MenuAdvanced Acpi Configuration Sub-Menu Chipset Acpi Configuration Sub-MenuShows Acpi configuration options Acpi Configuration Sub-MenuChipset Acpi Configuration Sub-Menu System Management Sub-MenuShows the System Management information Apic Acpi SCI IRQSystem Management Sub-Menu Event Log Configuration Sub-MenuShows event log configuration options PCI Express Error Masking Configuration Sub-Menu PCI Express Error Masking Configuration Sub-MenuEvent Log Configuration Sub-Menu MPS Configuration Sub-Menu Shows MPS Configuration optionsMPS Configuration Sub-Menu AdvancedTCA* Channel Routing PICMG* Sub-MenuOn-board Devices Configuration Sub-Menu AdvancedTCA Channel Routing Picmg Sub-MenuPCI Express* Configuration Sub-Menu Shows On-board Devices Configuration optionsOn-board Devices Configuration Sub-Menu Option ROM Configuration OptionsPCI Express* Configuration Sub-Menu Remote Access Configuration Sub-MenuShows PCI Express configuration options Remote Access Configuration Sub-Menu Ipmi Configuration Sub-MenuShows remote access configuration options Shows the Ipmi configuration options Ipmi Configuration Sub-MenuShows the LAN configuration options LAN Configuration Sub-MenuUSB Configuration Sub-Menu USB Configuration Sub-MenuShows USB configuration options USB Mass Storage Device Configuration USB Mass Storage Device ConfigurationPCIPnP Menu PCIPnP MenuBoot Menu Boot Settings Configuration Sub-MenuBoot Menu Shows Boot Settings Configuration optionsBoot Device Priority Sub-Menu Boot Settings Configuration Sub-Menu Sheet 2Shows Boot Device Priority options Boot Device Priority Sub-MenuOS Load Timeout Timer Sub-Menu Shows OS Load Timeout Timer optionsHard Disk Drives Sub-menu Shows Hard Disk Drives optionsOS Load Timeout Timer Sub-Menu Shows passwords and security featuresSecurity Menu Chipset MenuNorthbridge Configuration Sub-Menu Describes the sub-menus used to select chipset featuresNorthbridge Chipset Configuration Chipset MenuSpread Spectrum Clocking Mode Sub-Menu Spread Spectrum Clocking Mode ConfigurationExit Menu Exit MenuExit Menu Error Messages Bios Error MessagesBios Error Messages Cmos Checksum BAD Clear Cmos Jumper enabledBootblock Initialization Code Checkpoints Post Code CheckpointsCheckpoint Description SmramEarly CPU Init Exit DIM Code Checkpoints Acpi Runtime CheckpointsPCI Configuration Map PCI Configuration MapAddressing Lists the PCI devices and the bus on which they resideAMC B2 AMC B1 Fpga Register Legend Symbol DescriptionFpga Registers Extended Post Codes 0081h Fpga Register OverviewPost Codes 0080h Fpga Version 0A00h Version Programmable logic versionDebug LED 0A01h Address ActionDevelopment Features 0A04h Fwum 0A02hFwum Ready Fwum Busy PCB PCB versionTelecom Clock Register 0 0A08h Hwmode Holos MS2 MS1 Refalign FCS E3DS3Telecom Clock Register 1 0A09h Telecom Clock Register 2 0A0AhTelecom Clock Register 3 0A0Bh Transmission Frequency SelectionTelecom Clock Register 4 0A0Ch TXREFxSEL2..0 Transmission Clock FrequencyUnlock Hldovr SEC10 SEC01 PRI10 PRI01 0xA0D Write ResetTelecom Clock Register 6 0A0Eh Ipmc Addresses Telecom Clock Register 7 0A0FhIpmc Register Legend Address FunctionHT0 SBC Control 00hLtype Ltest Uart Brst PwrBtn usage SBC Status 01h Post Code Low 02hPost Code High 03h LED Color Control 06hAdvancedMC B1 Control & Status 10h AdvancedMC B1 Control & Status 11hAMC B2 Control & Status 12h AdvancedMC B2 Control & Status 13hCPU 0 VIDs 18h ADC Grab Control 20hVID5 VID4 VID3 VID2 VID1 VID0 Mcerr HOT Trip VTT IerrPCB 3VOC ADC1 and ADC2 Grab Data 21-22hFabric Control 1 24h Reset Source 27h Default configuration connects FWH0 and FWH1 to the ICHReset Events 29h Fabric Control 2 25hCrosspoint Switch Control 2Ah Crosspoint Switch Ports Register Crosspoint Switch Data 2BhMiscellaneous Controls and Status 2Dh Ipmc Post Codes FEhAddress Action FFh Read Reserved Version Write PowerUp Version FFhHardware Management Overview Intelligent Platform Management Controller IpmcIpmc Block Diagram Sensor Data Record SDR Hardware Sensors Sheet 1Green to Red State M1Hardware Sensors Sheet 2 Hardware Sensors Sheet 3 OEM Name OEM Number Description Hardware Sensors Sheet 4OEM Sensor Types System Event Log SEL OEM Event/Reading TypeSEL Events Supported Sheet 1 Sensor Sensor Type Specific Event Description CodeSEL Events Supported Sheet 2 PCI SerrPCI Perr SO/GOSEL Events Supported Sheet 3 When name is FIA FRU Initialization SEL Events Supported Sheet 4OEM SEL Events Supported Sheet 5Sensor Sensor Type Specific Event Description Code Offset Ipmb Link Sensor Field Replaceable Unit FRU InformationVariable Size Data Type Bytes ASC-IIFRU Customer Area Customizable FRU AreaLinuxCustFru Utility Usage Example 1. Input File SeecommonAB AC AD AE AF OEM Ipmi Commands KeyingReset Bios Flash Type Reset Bios Flash TypeBoard Device Channel Port Selection Identifiers Channel Port Selection IdentifiersResponse SetBoardDeviceChannelPortSelectionSetBoardDeviceChannelPortSelection GetBoardDeviceChannelPortSelection GetBoardDevicePossibleSelectionGetBoardDeviceChannelPortSelection GetBoardDevicePossibleSelectionSet Control State Get Control StateControls Identifier Table Set Control StateHot Swap Process Controls IdentifierControl Description Control Number FWHHot Swap LED Signals AdvancedMC Module ActivationHot Swap LED LED Status MeaningTemperature and Voltage Sensors Pre-Defined Resources for AdvancedMC ModulesSensors and Thresholds Version SDR System Firmware Progress Post Error System Acpi Power StateProcessor Events Dimm Memory EventsReset Reset ActionsReset Action System Function Memory Status Ipmb Link SensorWarm Reset Hard ResetIpmc Firmware Code Ipmc Firmware Code Process MPCBL0010 SBC-Hardware Management Overview Serial Over LAN SOL ReferencesSOL Architecture SOL ImplementationSOL Block Diagram Theory of Operation Architectural ComponentsFront Panel Serial Port or Rear Transition Module Serial Over LANReference Configuration Script Serial Over LAN ClientConfiguring the Blade for SOL Supported Usage ModelSOL Configuration Reference Script referencecfg Default BehaviorReference Script referencecfg SOL User InformationCommand Line Options SOL Configuration Reference Script Command-line OptionsSOL Parameters Channel ParametersBios Configuration Setting up a Serial Over LAN SessionTarget Blade Setup Operating System Configuration Change the serial parameter to readChange the kernel line to read For RhelSbcutils RPM Installation Execute the referencecfg ScriptExecute this command to configure SOL on the target blade Script executed on the Intel CMMClient Blade Setup Configure the Ethernet PortExecute this command to restart the network For RedHat* Rhel Configure IP address of the Ethernet portStart an SOL Session Installing ipmitoolChecking SOL Configuration Ending an SOL Session OEMOperating Systems for SOL Client ipmitool Block Diagram of the Telecom Clock Telecom ClockInterface Description Function DescriptionRecovered Clock Selection ConfigurationAlarm Handling Operational ConfigurationEnable/Disable Transmission Clock Telecom Clock APIModule Transmission Frequency Selection Name Used For ValueRecovered Clock Automatic SwitchoverAutomatic Switchover Mode Automatic Switchover ValuesPrimary/Secondary Redundant Clock Select Reference ClockReference Frequency for PLL PLL Operating Mode Hardware ResetCorner Frequency Reference Clock AlignmentRead Alarm States Hardware Reset ValuesAlarm State Values Read New EventsRead the Current Reference Clock Sysfs InterfaceReference Clock Values Telecom Clock API Function Mapping for the sysfs InterfaceA10-A1Fh Telecom Clock Registers80h October Technical Product Specification Order Number 171 DRVCLKB1 DRVCLKA1 DRVCLKB0 DRVCLKA0 Addres Action UNLOCK10 UNLOCK01 HLDOVR10 HLDOVR01 SEC10 SEC01 PRI10 PRI01 October Technical Product Specification Order Number 175 FPGA/PLD Serial Link Bit Definition Bit Write ReadMaintenance DiagnosticsSupervision In-Target Probe ITPPower vs. Flow Rate ThermalsComponent Technology For the Americas Warranty InformationReturning a Defective Product RMA Limitation of Liability and Remedies For Europe, Middle East, and Africa EmeaFor Asia and Pacific Apac MPCBL0010 SBC-Warranty Information Technical Support and Return for Service Assistance Customer SupportCustomer Support Sales AssistanceCertifications Vcci CisprzzJapan Vcci Class B Agency Information-Class BNorth America FCC Class B Korean Class B Australia, New Zealand Safety Warnings Mesures de Sécurité Sicherheitshinweise Norme di Sicurezza Instrucciones de Seguridad Chinese Safety Warning Appendix a Reference Documents MPCBL0010 SBC-Reference Documents Appendix B List of Supported Commands Ipmi v1.5 and Picmg Ipmi 1.5 Supported Commands Sheet 1Ipmi 1.5 Supported Commands Sheet 2 FRU Device Commands NetFnPicmg 3.0 Ipmi Supported Commands Command NetFn Interface