Intel MPCBL0010 manual Fpga Version 0A00h, Version Programmable logic version, Debug LED 0A01h

Page 98

Addressing—MPCBL0010 SBC

Note: POST codes are not always 16-bit and the high byte in register 81h could be unrelated to the content of register 80h. Also, only a 16-bit Write to I/O 80h will write to I/O 81h. An 8-bit Write to I/O 81h is ignored.

Table 70.

FPGA Version 0A00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

Action

D7

D6

 

D5

 

D4

 

D3

 

D2

 

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

 

 

 

Version

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xA00

Write

Reserved

 

 

 

NU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

Version

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Version: Programmable logic version.

 

 

 

 

 

 

 

 

 

 

 

Table 71.

Debug LED 0A01h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

Action

D7

D6

 

D5

 

D4

 

D3

 

D2

 

D1

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

MfgFlag

RJ45

 

EnHD

 

EnPost

 

EnClk

 

Green0

 

Amber0

Red0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xA01

Write

MfgFlag

RJ45

 

EnHD

 

EnPost

 

EnClk

 

Green0

 

Amber0

Red0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0/NA

1

 

0

 

1

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EnHD: Setting this bit uses LED Amber0 for displaying hard disk activity.

EnPost: Enables using the debug LED to display the last POST code of the boot. The BIOS clears this bit prior to the operating system launch.

EnClk: Enables telecom clock monitoring on the debug LED. EnHD and EnPost must be cleared. When the LED is green, both clocks are present. When the LED is amber, only one clock is present. When the LED is red, no clock is present or the Telco Clock PLD is not initialized. This is a debug mode.

Green0/Red0/Amber0: Debug LED 0. Used as a debug LED or to display POST codes (default during boot) or hard disk activity (default following boot) or as an end-user status/debug LED.

RJ45: This bit tells the FPGA which LEDs should reflect LAN activity; RJ-45 LEDs or grouped LEDs. The BIOS should set this bit as soon as possible to reflect the configuration of the fabric LAN. This should be set to 0 if the LAN goes to the fabric.

MfgFlag: A memory element used by the BIOS and test software in manufacturing.

Note: Tthis bit is cleared on a power-up, but is not affected by a reset

The Debug LED is amber/green when in Reset (this is hardware). As soon as the FPGA is programmed, the LED is amber and is enabled for POST code display. If the BIOS fails, it is possible to read the POST code. If the BIOS succeeds, it disables the POST code and enables HD activity on the green LED. If needed, the application software can then disable hard disk activity reporting and directly control the bi-color LED for status reporting.

To read the 8-bit POST code:

Both colors: Start of POST sequence.

Amber blink: This is the high nibble. 0 to 15 blinks represent hexadecimal 0 to F.

Green blink: This is the low nibble. 0 to 15 blinks represent hexadecimal 0 to F.

 

Intel NetStructure® MPCBL0010 Single Board Computer

October 2006

Technical Product Specification

Order Number: 304120

97

Image 98
Contents Technical Product Specification Intel NetStructure MPCBL0010 Single Board ComputerOrder Number Contents 1.2 Weight1.1 1.3PwrBtn usage 10.8 OEM Ipmi Commands10.8.1 Reset Bios Flash Type Hardware Management Overview10.8.2.1 10.8.2131 132178 Component Technology 179 Warranty Information 180 16.1177 AdvancedMC Direct Connect Switch Block Diagram Safety Warnings20.5 Chinese Safety Warning Warm Reset Block DiagramSupported Memory Configurations Jumper Definitions Tables102 100101 103Reset Actions 140 Reset Bios Flash Type 131Hot Swap LED Signals 136 SOL Configuration Reference Script Command-line Options 151Revision History Date Revision DescriptionIntroduction Document OrganizationGlossary See the Low Pin Count LPC Interface specification That allows your networked client computer to boot using aIntelligent Platform Management Bus. Physical two-wire Phase-locked LoopFunctional Description Feature OverviewApplication Low Voltage Intel Xeon Processor Chipset2.2 I/O Controller Hub Memory J10, J12Memory Controller Hub 2.3 64-Bit PCI Hub4 I/O TimersSupported Memory Configurations 4.1 I/O Controller Hub4.5 10/100 Fast Ethernet AdvancedMC AMC Connector J18, J19Gigabit Ethernet 4.6 USB6.1 FWH0 Main Bios Firmware HubsFlash ROM Backup Mechanism Onboard Power Supplies6.2 FWH1 Backup/Recovery Bios Power Feed FusesIpmc Telecom ClockAdvancedMC Direct Connect AdvancedMCA Direct Connect Switch Block Diagram AdvancedTCA ComplianceOperating the Unit JumpersName Function with Jumper Present On Removed Off MPCBL0010 SBCAdvancedMC Filler Panels AdvancedMC Filler PanelInstalling Memory Remove the coverInstalling and Extracting the SBC Insert two matched pair DIMMsChassis Installation Chassis ExtractionSolid blue Remote Access Configuration AdvancedMC Module Installation and ExtractionBios Configuration Software UpdatesBios Image Command Behavior Bios UpdatesLoading\Saving Custom Bios Configuration Copying BIOS.bin from the SBC Saving BIOS.bin to the SBCIpmc Firmware Upgrade Using the KCS Interface Ipmc Firmware UpdatesFlashlnx Command Line Options Flashlnx Utility Command Line OptionsDigital Ground and Chassis Ground Isolated Default Digital Ground to Chassis Ground ConnectivityEnvironmental Specifications SpecificationsMechanical Specifications Board OutlineEnvironmental Assumptions Reliability SpecificationsMean Time Between Failure Mtbf Specifications General AssumptionsPower Consumption WeightPower Requirements General NotesConnectors and LEDs Connectors and LEDs-MPCBL0010 SBC Backplane Description ConnectorsFront Panel Front Panel Connector Assignments Front Panel Description ConnectorsBackplane Connectors Power Distribution Connector P10Pin Signal Description AdvancedTCA Data Transport Connector J23Power Distribution Connector Zone 1 P10 Pin Assignments Data Transport Connector Zone 2 J23 Alignment Blocks AdvancedTCA Data Transport Connector J20AdvancedTCA* Data Transport Connector Zone 2 J20 Pin PinExtended IPT700 Debug Port Connector J25 On-Board ConnectorsPost Code Connector J13 Post Code Connector Pin AssignmentsEthernet 10/100 Debug Connector LED Operation Front Panel ConnectorsEthernet 10/100 Debug Connector J3 FunctionUSB Connector J4 Serial Port Connector J5AdvancedMC* Connectors J18, J19 Serial Port Connector J5 Pin AssignmentsAdvancedMC* Connector Pin Assignments AdvancedMC* Connector LEDsOOS Front Panel LED Descriptions Sheet 1 OOSPost LED Codes Front Panel LED Descriptions Sheet 2Reset Button Example Post LED CodesRedundant Bios Functionality Bios FeaturesBios Flash Memory Organization IntroductionLegacy USB Support Recovering Bios DataBoot Options Language SupportCD-ROM and Network Boot Fast Booting SystemsBios Security Features Booting without Attached DevicesKey Escape Sequence Supervisor and User Password FunctionsFunction Key Escape Code Equivalents Sheet 1 ESC OP ESC OQ ESC or ESC OSESC OY Function Key Escape Code Equivalents Sheet 2ESC OW ESC OX ESC OZBios Setup Program Function Keys Bios SetupBios Setup Program Menu Bar Main MenuAdvanced Menu Feature Options DescriptionBios ID Main MenuPicmg CPU Configuration Sub-MenuAdvanced Menu CPU Configuration Sub-Menu IDE Configuration Sub-MenuShows the sub-menu options for configuring the CPU Shows the IDE configuration options IDE Configuration Sub-MenuIDE Master/Slave Sub-Menu Primary IDE Master/Slave Configuration OptionsShows the IDE Master/Slave configuration options SuperIO Configuration Sub-Menu Shows SuperIO configuration optionsAcpi Configuration Sub-Menu SuperIO Configuration Sub-MenuShows Acpi configuration options Advanced Acpi Configuration Sub-MenuChipset Acpi Configuration Sub-Menu Acpi Configuration Sub-MenuShows the System Management information Chipset Acpi Configuration Sub-MenuSystem Management Sub-Menu Apic Acpi SCI IRQSystem Management Sub-Menu Event Log Configuration Sub-MenuShows event log configuration options PCI Express Error Masking Configuration Sub-Menu PCI Express Error Masking Configuration Sub-MenuEvent Log Configuration Sub-Menu MPS Configuration Sub-Menu MPS Configuration Sub-MenuShows MPS Configuration options AdvancedTCA* Channel Routing PICMG* Sub-MenuOn-board Devices Configuration Sub-Menu AdvancedTCA Channel Routing Picmg Sub-MenuOn-board Devices Configuration Sub-Menu PCI Express* Configuration Sub-MenuShows On-board Devices Configuration options Option ROM Configuration OptionsPCI Express* Configuration Sub-Menu Remote Access Configuration Sub-MenuShows PCI Express configuration options Remote Access Configuration Sub-Menu Ipmi Configuration Sub-MenuShows remote access configuration options Shows the LAN configuration options Shows the Ipmi configuration optionsIpmi Configuration Sub-Menu LAN Configuration Sub-MenuUSB Configuration Sub-Menu USB Configuration Sub-MenuShows USB configuration options PCIPnP Menu USB Mass Storage Device ConfigurationUSB Mass Storage Device Configuration PCIPnP MenuBoot Menu Boot MenuBoot Settings Configuration Sub-Menu Shows Boot Settings Configuration optionsShows Boot Device Priority options Boot Device Priority Sub-MenuBoot Settings Configuration Sub-Menu Sheet 2 Boot Device Priority Sub-MenuHard Disk Drives Sub-menu OS Load Timeout Timer Sub-MenuShows OS Load Timeout Timer options Shows Hard Disk Drives optionsSecurity Menu OS Load Timeout Timer Sub-MenuShows passwords and security features Chipset MenuNorthbridge Chipset Configuration Northbridge Configuration Sub-MenuDescribes the sub-menus used to select chipset features Chipset MenuExit Menu Spread Spectrum Clocking Mode Sub-MenuSpread Spectrum Clocking Mode Configuration Exit MenuExit Menu Bios Error Messages Error MessagesBios Error Messages Cmos Checksum BAD Clear Cmos Jumper enabledCheckpoint Description Bootblock Initialization Code CheckpointsPost Code Checkpoints SmramEarly CPU Init Exit DIM Code Checkpoints Acpi Runtime CheckpointsAddressing PCI Configuration MapPCI Configuration Map Lists the PCI devices and the bus on which they resideAMC B2 AMC B1 Fpga Register Legend Symbol DescriptionFpga Registers Extended Post Codes 0081h Fpga Register OverviewPost Codes 0080h Debug LED 0A01h Fpga Version 0A00hVersion Programmable logic version Address ActionFwum Ready Fwum Busy Development Features 0A04hFwum 0A02h PCB PCB versionTelecom Clock Register 0 0A08h Hwmode Holos MS2 MS1 Refalign FCS E3DS3Telecom Clock Register 1 0A09h Telecom Clock Register 2 0A0AhTelecom Clock Register 4 0A0Ch Telecom Clock Register 3 0A0BhTransmission Frequency Selection TXREFxSEL2..0 Transmission Clock FrequencyUnlock Hldovr SEC10 SEC01 PRI10 PRI01 0xA0D Write ResetTelecom Clock Register 6 0A0Eh Ipmc Register Legend Ipmc AddressesTelecom Clock Register 7 0A0Fh Address FunctionHT0 SBC Control 00hLtype Ltest Uart Brst PwrBtn usage Post Code High 03h SBC Status 01hPost Code Low 02h LED Color Control 06hAdvancedMC B1 Control & Status 10h AdvancedMC B1 Control & Status 11hAMC B2 Control & Status 12h AdvancedMC B2 Control & Status 13hVID5 VID4 VID3 VID2 VID1 VID0 CPU 0 VIDs 18hADC Grab Control 20h Mcerr HOT Trip VTT IerrPCB 3VOC ADC1 and ADC2 Grab Data 21-22hFabric Control 1 24h Reset Events 29h Reset Source 27hDefault configuration connects FWH0 and FWH1 to the ICH Fabric Control 2 25hCrosspoint Switch Control 2Ah Miscellaneous Controls and Status 2Dh Crosspoint Switch Ports RegisterCrosspoint Switch Data 2Bh Ipmc Post Codes FEhAddress Action FFh Read Reserved Version Write PowerUp Version FFhHardware Management Overview Intelligent Platform Management Controller IpmcIpmc Block Diagram Green to Red Sensor Data Record SDRHardware Sensors Sheet 1 State M1Hardware Sensors Sheet 2 Hardware Sensors Sheet 3 OEM Name OEM Number Description Hardware Sensors Sheet 4OEM Sensor Types SEL Events Supported Sheet 1 System Event Log SELOEM Event/Reading Type Sensor Sensor Type Specific Event Description CodePCI Perr SEL Events Supported Sheet 2PCI Serr SO/GOSEL Events Supported Sheet 3 When name is FIA FRU Initialization SEL Events Supported Sheet 4OEM SEL Events Supported Sheet 5Sensor Sensor Type Specific Event Description Code Offset Variable Size Data Type Bytes Ipmb Link SensorField Replaceable Unit FRU Information ASC-IIFRU Customer Area Customizable FRU AreaLinuxCustFru Utility Usage Example 1. Input File SeecommonAB AC AD AE AF OEM Ipmi Commands KeyingBoard Device Channel Port Selection Identifiers Reset Bios Flash TypeReset Bios Flash Type Channel Port Selection IdentifiersResponse SetBoardDeviceChannelPortSelectionSetBoardDeviceChannelPortSelection GetBoardDeviceChannelPortSelection GetBoardDeviceChannelPortSelectionGetBoardDevicePossibleSelection GetBoardDevicePossibleSelectionControls Identifier Table Set Control StateGet Control State Set Control StateControl Description Control Number Hot Swap ProcessControls Identifier FWHHot Swap LED Hot Swap LED SignalsAdvancedMC Module Activation LED Status MeaningTemperature and Voltage Sensors Pre-Defined Resources for AdvancedMC ModulesSensors and Thresholds Version SDR Processor Events System Firmware Progress Post ErrorSystem Acpi Power State Dimm Memory EventsReset Action System Function Memory Status ResetReset Actions Ipmb Link SensorWarm Reset Hard ResetIpmc Firmware Code Ipmc Firmware Code Process MPCBL0010 SBC-Hardware Management Overview SOL Architecture Serial Over LAN SOLReferences SOL ImplementationSOL Block Diagram Front Panel Serial Port or Rear Transition Module Theory of OperationArchitectural Components Serial Over LANReference Configuration Script Serial Over LAN ClientConfiguring the Blade for SOL Supported Usage ModelReference Script referencecfg SOL Configuration Reference Script referencecfgDefault Behavior SOL User InformationSOL Parameters Command Line OptionsSOL Configuration Reference Script Command-line Options Channel ParametersBios Configuration Setting up a Serial Over LAN SessionTarget Blade Setup Operating System Configuration Change the serial parameter to readChange the kernel line to read For RhelSbcutils RPM Installation Execute the referencecfg ScriptExecute this command to configure SOL on the target blade Script executed on the Intel CMMExecute this command to restart the network Client Blade SetupConfigure the Ethernet Port For RedHat* Rhel Configure IP address of the Ethernet portStart an SOL Session Installing ipmitoolChecking SOL Configuration Ending an SOL Session OEMOperating Systems for SOL Client ipmitool Block Diagram of the Telecom Clock Telecom ClockInterface Description Function DescriptionAlarm Handling Recovered Clock SelectionConfiguration Operational ConfigurationModule Transmission Frequency Selection Enable/Disable Transmission ClockTelecom Clock API Name Used For ValueAutomatic Switchover Mode Recovered ClockAutomatic Switchover Automatic Switchover ValuesPrimary/Secondary Redundant Clock Select Reference ClockReference Frequency for PLL Corner Frequency PLL Operating ModeHardware Reset Reference Clock AlignmentAlarm State Values Read Alarm StatesHardware Reset Values Read New EventsReference Clock Values Read the Current Reference ClockSysfs Interface Telecom Clock API Function Mapping for the sysfs InterfaceA10-A1Fh Telecom Clock Registers80h October Technical Product Specification Order Number 171 DRVCLKB1 DRVCLKA1 DRVCLKB0 DRVCLKA0 Addres Action UNLOCK10 UNLOCK01 HLDOVR10 HLDOVR01 SEC10 SEC01 PRI10 PRI01 October Technical Product Specification Order Number 175 FPGA/PLD Serial Link Bit Definition Bit Write ReadSupervision MaintenanceDiagnostics In-Target Probe ITPPower vs. Flow Rate ThermalsComponent Technology For the Americas Warranty InformationReturning a Defective Product RMA Limitation of Liability and Remedies For Europe, Middle East, and Africa EmeaFor Asia and Pacific Apac MPCBL0010 SBC-Warranty Information Customer Support Technical Support and Return for Service AssistanceCustomer Support Sales AssistanceCertifications Vcci CisprzzJapan Vcci Class B Agency Information-Class BNorth America FCC Class B Korean Class B Australia, New Zealand Safety Warnings Mesures de Sécurité Sicherheitshinweise Norme di Sicurezza Instrucciones de Seguridad Chinese Safety Warning Appendix a Reference Documents MPCBL0010 SBC-Reference Documents Appendix B List of Supported Commands Ipmi v1.5 and Picmg Ipmi 1.5 Supported Commands Sheet 1Ipmi 1.5 Supported Commands Sheet 2 FRU Device Commands NetFnPicmg 3.0 Ipmi Supported Commands Command NetFn Interface