Konica Minolta PCI-1712L user manual Post-Trigger Acquisition Mode

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Chapter 5

Trigger Event

Acquired number of samples N

1st

2nd

3rd

N-2th N-1th Nth

 

 

 

t

Figure 5-1: Post-Trigger Acquisition Mode

qDelay Trigger Acquisition Mode

In delay trigger mode, data acquisition will be activated after a preset delay number of sample has been taken after the trigger event. The delay number of sample ranges from 2 to 65535 as defined in DMA counter.

Delay-trigger acquisition starts when the PCI-1712/1712L detects the trigger event and stops when the specified number of A/D samples has been acquired or when you stop the operation. This triggering mode must work with the DMA data transfer mode enabled

Please specify the following parameters when using software in delay trigger mode:

wSet to Delay-Trigger Acquisition Mode

wThe sample clock source and sampling rate

wThe trigger source and edge type

wThe acquired sample number N

wThe sample number M delays after the delay-trigger event hap- pened

Trigger Event

Delay time M:

from 2 to 65535 samples

1 2 3

M-2 M-1 M

Acquired number of samples N

1st 2nd 3rd

N-2 N-1 N

t

Figure 5-2: Delay-Trigger Acquisition Mode

qAbout Trigger Acquisition Mode

Use about-trigger acquisition mode when you want to acquire data both before and after a specific trigger event occurs. This operation is equivalent to doing both a pre-trigger and a post-trigger acquisition. When using software, please specify the following parameters, when using software in About-Trigger acquisition mode:

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PCI-1712/1712L User’s Manual

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Page 46 Page 48
Contents MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Appendix D. Register Structure and Format Calibration100 Figures Auto A/D Calibration Dialog Box Table D-3 I/O Connector Signal Description PartCorresponding Full Scale values for various Input Table D-1PCI-1712/1712L register format Part Table D-2102 100101 Page Introduction FeaturesAutomatic Channel/Gain/SD*/BU* Scanning PCI-Bus Mastering Data TransferPlug-and-Play Function On-board Fifo MemoryContinuous Analog Output Installation GuideOn-board Programmable Multifunction Counter/Timer Installation Flow Chart Wiring Boards AccessoriesWiring Cable Chapter Unpacking InstallationSetup Screen of Advantech Automation Software Driver InstallationDifferent options for Driver Setup Hardware InstallationChapter Device name listed on the Device Manager Setting Up the Device Device Setup & ConfigurationDevices Found dialog box Configuring the DeviceFor bipolar For unipolarTesting Analog Input Function Device TestingTesting Digital Input Function Testing Analog Output Function PCI-1712 onlyTesting Counter Function Testing Digital Output Function14 Digital output tab on the Device Test dialog box Pin Assignment Signal ConnectionsI/O Connector OverviewI/O connector pin assignments for the PCI-1712/1712L I/O Connector Signal Description Part Connector Signal DescriptionSignal Name Reference Direction Description Counter 0 Gate Input. This pin is for Differential Channel Connections Analog Input ConnectionsSingle-ended Channel Connections Chapter Differential input channel connection floating signal Source Analog output connections Analog Output ConnectionsField Wiring Considerations Register-level Programming Software OverviewProgramming Choices DLL DriverProgramming Tools DLL Driver Programming RoadmapProgramming with DLL Driver Function Library Troubleshooting DLL Driver ErrorChapter Gains and Analog Input Range Analog Input FeaturesPrinciples of Operation Analog Input Ranges and GainsAnalog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Sample Clock Sources Pre-Trigger Acquisition ModeTrigger Sources PCI-1712/1712L Sample Clock SourceAnalog Input Data Format Analog Input Data FormatAnalog Output Operation Modes Analog Output FeaturesAnalog Output Ranges Output Clock Sources Trigger Sources Analog Output Data Format Digital I/O FeaturesAnalog Output Data Format Clock sources Counter/Timer FeaturesGate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive VR Assignment CalibrationA/D Calibration D/A Calibration Selecting the device you want to calibrate Calibration UtilityAuto A/D Calibration Dialog Box Channel Auto-CalibrationA/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel 13 Selecting Input Rage in Manual A/D Calibration panel Channel Manual-Calibration14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Analog Input SpecificationDigital Input /Output Analog Output PCI-1712 onlyGeneral Counter/TimerAppendix a Block Diagram Block DiagramAppendix B Board Layout Screw-terminal BoardFigure C-2 CN2 pin assignments for the PCLD-8712 Pin AssignmentSingle-ended Connections Differential Connections I/O Port Address Map Register Structure and FormatTable D-1 PCI-1712/1712L register format Part Appendix DBase PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W CH2 to CH0 Channel Number A/D Single Value Acquisition Write BASE+0Channel and A/D data Read Base + Data of A/D ConversionBipolar or Unipolar A/D Channel Range Setting Write BASE+2Table D-3 Register for A/D channel range setting Single-ended or DifferentialStart Scan Channel Number MUX Control Write BASE+4Table D-4 Gain Codes for the PCI-1712/1712L Table D-5 Register for multiplexer controlAppendix D Table D-6 Register for A/D control/status Analog input acquisition mode registerA/D Control/Status Register Write/Read BASE+6 Analog I/O calibration bit Sample clock source select registerTrigger source control register Trigger edge control registerClear A/D Fifo Clear interrupt and Fifo Write BASE+8Aitrgf Analog input trigger flag Table D-8 Register for clear interrupt and FifoFifo half-full flag Interrupt and Fifo status Read BASE+8Interrupt flag Fifo empty flag10 D/A control/status register Write/Read BASE+A Aotrgf Analog output trigger flag Table D-11 Analog output operation modeChannel 1 unipolar or bipolar output Clock source select registerData 11 D/A Channel 0/1 Data Write BASE+C/ETable D-12 Register for D/A channel 0/1 data Table D-13 Register for 82C54 counter chip 12 82C54 Counter Chip 0 Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip 13 82C54 counter chip 1 Write/Read BASE+18 to 1ETable D-16 Table of Cn1 to Cn0 register Cn1 to Cn0 Counter clock source control register n = 0,1,2Table D-17 Table of Gn1 to Gn0 register CPn Counter clock edge control register n = 0,1,2CQn Counter clock set register n = 0,1,2 Gn1 to Gn0 Counter gate source control register n = 0,1,2GATEn Gate status n = 0,1,2 GRn Pulse width measurement reset register n = 0,1,2GPn Counter gate polarity control register n = 0,1,2 GQn Counter gate set register n = 0,1,2DO15 to DO0 Digital output data register Digital I/O registers Write/Read BASE+28GATESn Pulse width measurement status bit n = 0,1,2 CLKSEL1 & 0 Counter internal clock select registerDI15 to DI0 Digital input data register Digital I/O configuration registers Write/Read BASE+2ACalibration command registers Write BASE+2C DIOC1 to DIOC0 Digital I/O configuration registerD7 to D0 Calibration data CM3 to CM0 Calibration commandTable D-23 Calibration command DA11 to DA0 D/A data Table D-24 Register for D/A channel data

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