Konica Minolta PCI-1712L user manual Gate Types and Sources

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Chapter 5

0, 1 and 2. You can choose any counter to be your first cascaded counter, and the next counter would the next one in the round-robin order. For example, if you would like to cascade two 16-bit counters into one 32-bit counter, and you choose counter 1 to be the first counter then the next counter you choose should be counter 2.

Gate Types and Sources

The gate types and sources you select determine what kind of gate input signal to enable your counter/timer when receiving clock input. If the external gate input signal comes in either as logic-low or logic-high as you have preset, the counter/timer function is enabled, waiting only for the clock input signal to start counting. The PCI-1712/1712L provides two gate input types, for which user can set easily through software or write to bit GPn on register Base+20 to 24:

qLogic-low external gate input:

Enables a counter/timer operation when the external gate signal is logic-low, and disables the counter/timer operation when the external gate signal is logic-high.

qLogic-high external gate input:

Enables a counter/timer operation when the external gate signal is logic-high and disables the counter/timer operation when the external gate signal is logic-low.

The gate sources are described as below:

qSoftware Gate:

User can use software to generate the signal to be counter’s gate input. It helps user to control counter easily through software.

qPrevious Counter Output:

User can use previous counter’s output as your gate source. The previous counter of counter 0 is counter 2, of counter 1 is counter 0 and of counter 2 is counter 1.

qExternal Gate Source:

User can connect an external gate signal to screw terminal

CNTn_GATE on the PCLD-8712 screw terminal board, where n is the counter number.

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PCI-1712/1712L User’s Manual

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Contents MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Appendix D. Register Structure and Format Calibration100 Figures Auto A/D Calibration Dialog Box Corresponding Full Scale values for various Input I/O Connector Signal Description PartTable D-1PCI-1712/1712L register format Part Table D-2 Table D-3100 101102 Page Introduction FeaturesPlug-and-Play Function PCI-Bus Mastering Data TransferOn-board Fifo Memory Automatic Channel/Gain/SD*/BU* ScanningInstallation Guide On-board Programmable Multifunction Counter/TimerContinuous Analog Output Installation Flow Chart Accessories Wiring CableWiring Boards Chapter Unpacking InstallationSetup Screen of Advantech Automation Software Driver InstallationDifferent options for Driver Setup Hardware InstallationChapter Device name listed on the Device Manager Setting Up the Device Device Setup & ConfigurationDevices Found dialog box Configuring the DeviceFor bipolar For unipolarTesting Analog Input Function Device TestingTesting Digital Input Function Testing Analog Output Function PCI-1712 onlyTesting Counter Function Testing Digital Output Function14 Digital output tab on the Device Test dialog box I/O Connector Signal ConnectionsOverview Pin AssignmentI/O connector pin assignments for the PCI-1712/1712L I/O Connector Signal Description Part Connector Signal DescriptionSignal Name Reference Direction Description Counter 0 Gate Input. This pin is for Analog Input Connections Single-ended Channel ConnectionsDifferential Channel Connections Chapter Differential input channel connection floating signal Source Analog output connections Analog Output ConnectionsField Wiring Considerations Programming Choices Software OverviewDLL Driver Register-level ProgrammingProgramming Tools DLL Driver Programming RoadmapProgramming with DLL Driver Function Library Troubleshooting DLL Driver ErrorChapter Principles of Operation Analog Input FeaturesAnalog Input Ranges and Gains Gains and Analog Input RangeAnalog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Sample Clock Sources Pre-Trigger Acquisition ModeTrigger Sources PCI-1712/1712L Sample Clock SourceAnalog Input Data Format Analog Input Data FormatAnalog Output Features Analog Output RangesAnalog Output Operation Modes Output Clock Sources Trigger Sources Digital I/O Features Analog Output Data FormatAnalog Output Data Format Clock sources Counter/Timer FeaturesGate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive VR Assignment CalibrationA/D Calibration D/A Calibration Selecting the device you want to calibrate Calibration UtilityAuto A/D Calibration Dialog Box Channel Auto-CalibrationA/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel 13 Selecting Input Rage in Manual A/D Calibration panel Channel Manual-Calibration14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Analog Input SpecificationDigital Input /Output Analog Output PCI-1712 onlyGeneral Counter/TimerAppendix a Block Diagram Block DiagramAppendix B Board Layout Screw-terminal BoardFigure C-2 CN2 pin assignments for the PCLD-8712 Pin AssignmentSingle-ended Connections Differential Connections I/O Port Address Map Register Structure and FormatTable D-1 PCI-1712/1712L register format Part Appendix DBase PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W Channel and A/D data Read Base + A/D Single Value Acquisition Write BASE+0Data of A/D Conversion CH2 to CH0 Channel NumberTable D-3 Register for A/D channel range setting A/D Channel Range Setting Write BASE+2Single-ended or Differential Bipolar or UnipolarTable D-4 Gain Codes for the PCI-1712/1712L MUX Control Write BASE+4Table D-5 Register for multiplexer control Start Scan Channel NumberAppendix D Analog input acquisition mode register A/D Control/Status Register Write/Read BASE+6Table D-6 Register for A/D control/status Trigger source control register Sample clock source select registerTrigger edge control register Analog I/O calibration bitAitrgf Analog input trigger flag Clear interrupt and Fifo Write BASE+8Table D-8 Register for clear interrupt and Fifo Clear A/D FifoInterrupt flag Interrupt and Fifo status Read BASE+8Fifo empty flag Fifo half-full flag10 D/A control/status register Write/Read BASE+A Channel 1 unipolar or bipolar output Table D-11 Analog output operation modeClock source select register Aotrgf Analog output trigger flag11 D/A Channel 0/1 Data Write BASE+C/E Table D-12 Register for D/A channel 0/1 dataData Table D-13 Register for 82C54 counter chip 12 82C54 Counter Chip 0 Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip 13 82C54 counter chip 1 Write/Read BASE+18 to 1ETable D-16 Table of Cn1 to Cn0 register Cn1 to Cn0 Counter clock source control register n = 0,1,2CQn Counter clock set register n = 0,1,2 CPn Counter clock edge control register n = 0,1,2Gn1 to Gn0 Counter gate source control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerGPn Counter gate polarity control register n = 0,1,2 GRn Pulse width measurement reset register n = 0,1,2GQn Counter gate set register n = 0,1,2 GATEn Gate status n = 0,1,2GATESn Pulse width measurement status bit n = 0,1,2 Digital I/O registers Write/Read BASE+28CLKSEL1 & 0 Counter internal clock select register DO15 to DO0 Digital output data registerCalibration command registers Write BASE+2C Digital I/O configuration registers Write/Read BASE+2ADIOC1 to DIOC0 Digital I/O configuration register DI15 to DI0 Digital input data registerCM3 to CM0 Calibration command Table D-23 Calibration commandD7 to D0 Calibration data DA11 to DA0 D/A data Table D-24 Register for D/A channel data

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