Konica Minolta PCI-1712L user manual About-Trigger Acquisition Mode

Page 48

Chapter 5

wSet to About-Trigger Acquisition Mode

wThe sample clock source and sample rate

wThe trigger source and edge type

wThe total acquired sample number N

wThe specific sample number M before the trigger event. The range of preset sample number is 2 samples minimum and is limited on basis of memory size of your host PC.

In about-trigger mode, users must first designate the size of the allocated memory and the amount of samples to be snatched after the trigger event happens. The about-trigger acquisition starts when the first clock signal comes in. Once a trigger event happens, the on-going data acquisition will continue until the designated amount of samples have been reached. When the PCI-1712/1712L detects the selected about-trigger event, the card keeps acquiring the preset number of samples, and kept the total number of samples on the FIFO.

Trigger Event

Acquired number of

samples M after trigger

event happened

1

2

3

N-M

N

 

 

 

 

t

Total Acquired sample number: N

Figure 5-3: About-Trigger Acquisition Mode

qPre-Trigger Acquisition Mode

Pre-Trigger mode is a particular application of about-trigger mode. Use pre-trigger acquisition mode when you want to acquire data before a specific trigger event occurs. Pre-trigger acquisition starts when you start the operation and stops when the trigger event happens. Then the specific number of samples will be reversed in the FIFO before the pre-trigger event occurred. Please specify the following parameters, when using software in Pre-trigger acquisition mode:

wSet to Pre-Trigger Acquisition Mode

wThe sample clock source and sample rate

wThe trigger source and gate type

wAssume the total acquired sample number is N, then set the total sample number to be N+2.

PCI-1712/1712L User’s Manual

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Contents MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Calibration Appendix D. Register Structure and Format100 Figures Auto A/D Calibration Dialog Box I/O Connector Signal Description Part Corresponding Full Scale values for various InputTable D-1PCI-1712/1712L register format Part Table D-2 Table D-3100 101102 Page Features IntroductionPCI-Bus Mastering Data Transfer Plug-and-Play FunctionOn-board Fifo Memory Automatic Channel/Gain/SD*/BU* ScanningInstallation Guide On-board Programmable Multifunction Counter/TimerContinuous Analog Output Installation Flow Chart Accessories Wiring CableWiring Boards Chapter Installation UnpackingDriver Installation Setup Screen of Advantech Automation SoftwareHardware Installation Different options for Driver SetupChapter Device name listed on the Device Manager Device Setup & Configuration Setting Up the DeviceConfiguring the Device Devices Found dialog boxFor unipolar For bipolarDevice Testing Testing Analog Input FunctionTesting Analog Output Function PCI-1712 only Testing Digital Input FunctionTesting Digital Output Function Testing Counter Function14 Digital output tab on the Device Test dialog box Signal Connections I/O ConnectorOverview Pin AssignmentI/O connector pin assignments for the PCI-1712/1712L Connector Signal Description I/O Connector Signal Description PartSignal Name Reference Direction Description Counter 0 Gate Input. This pin is for Analog Input Connections Single-ended Channel ConnectionsDifferential Channel Connections Chapter Differential input channel connection floating signal Source Analog Output Connections Analog output connectionsField Wiring Considerations Software Overview Programming ChoicesDLL Driver Register-level ProgrammingDLL Driver Programming Roadmap Programming ToolsTroubleshooting DLL Driver Error Programming with DLL Driver Function LibraryChapter Analog Input Features Principles of OperationAnalog Input Ranges and Gains Gains and Analog Input RangeAnalog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Pre-Trigger Acquisition Mode Sample Clock SourcesPCI-1712/1712L Sample Clock Source Trigger SourcesAnalog Input Data Format Analog Input Data FormatAnalog Output Features Analog Output RangesAnalog Output Operation Modes Output Clock Sources Trigger Sources Digital I/O Features Analog Output Data FormatAnalog Output Data Format Counter/Timer Features Clock sourcesGate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive Calibration VR AssignmentA/D Calibration D/A Calibration Calibration Utility Selecting the device you want to calibrateChannel Auto-Calibration Auto A/D Calibration Dialog BoxA/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel Channel Manual-Calibration 13 Selecting Input Rage in Manual A/D Calibration panel14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Specification Analog InputAnalog Output PCI-1712 only Digital Input /OutputCounter/Timer GeneralAppendix a Block Diagram Block DiagramAppendix B Screw-terminal Board Board LayoutPin Assignment Figure C-2 CN2 pin assignments for the PCLD-8712Single-ended Connections Differential Connections Register Structure and Format I/O Port Address MapAppendix D Table D-1 PCI-1712/1712L register format PartBase PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W A/D Single Value Acquisition Write BASE+0 Channel and A/D data Read Base +Data of A/D Conversion CH2 to CH0 Channel NumberA/D Channel Range Setting Write BASE+2 Table D-3 Register for A/D channel range settingSingle-ended or Differential Bipolar or UnipolarMUX Control Write BASE+4 Table D-4 Gain Codes for the PCI-1712/1712LTable D-5 Register for multiplexer control Start Scan Channel NumberAppendix D Analog input acquisition mode register A/D Control/Status Register Write/Read BASE+6Table D-6 Register for A/D control/status Sample clock source select register Trigger source control registerTrigger edge control register Analog I/O calibration bitClear interrupt and Fifo Write BASE+8 Aitrgf Analog input trigger flagTable D-8 Register for clear interrupt and Fifo Clear A/D FifoInterrupt and Fifo status Read BASE+8 Interrupt flagFifo empty flag Fifo half-full flag10 D/A control/status register Write/Read BASE+A Table D-11 Analog output operation mode Channel 1 unipolar or bipolar outputClock source select register Aotrgf Analog output trigger flag11 D/A Channel 0/1 Data Write BASE+C/E Table D-12 Register for D/A channel 0/1 dataData 12 82C54 Counter Chip 0 Write/Read BASE+10 to Table D-13 Register for 82C54 counter chip13 82C54 counter chip 1 Write/Read BASE+18 to 1E Table D-14 Register for 82C54 counter chipCn1 to Cn0 Counter clock source control register n = 0,1,2 Table D-16 Table of Cn1 to Cn0 registerCPn Counter clock edge control register n = 0,1,2 CQn Counter clock set register n = 0,1,2Gn1 to Gn0 Counter gate source control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerGRn Pulse width measurement reset register n = 0,1,2 GPn Counter gate polarity control register n = 0,1,2GQn Counter gate set register n = 0,1,2 GATEn Gate status n = 0,1,2Digital I/O registers Write/Read BASE+28 GATESn Pulse width measurement status bit n = 0,1,2CLKSEL1 & 0 Counter internal clock select register DO15 to DO0 Digital output data registerDigital I/O configuration registers Write/Read BASE+2A Calibration command registers Write BASE+2CDIOC1 to DIOC0 Digital I/O configuration register DI15 to DI0 Digital input data registerCM3 to CM0 Calibration command Table D-23 Calibration commandD7 to D0 Calibration data Table D-24 Register for D/A channel data DA11 to DA0 D/A data

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