Konica Minolta PCI-1712L user manual Output Clock Sources

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Chapter 5

channel.

In this mode, users need to set the clock source and trigger source first, and then generate the output data to be stored in the memory buffers of host PC. The host computer then transfers those data to be written to the DACs from its buffers to the 32K-sample Output FIFO on board. When it detects a trigger, the board outputs the values in the Output FIFO to the DACs at the same time. When the samples in FIFO decreases to less than half size (i.e. 16K samples) of the FIFO, then the card will send a interrupt request to the host PC, which in turn sends 16K samples to the FIFO. This output operation will repeat until either all the data is sent from the buffers or until you stop the operation.

If the two D/A channels are both operating in continuous output mode, the data in FIFO will be sent in an interlaced manner, i.e. The “even” samples in the FIFO are sent to D/A channel 0, while the “odd” samples to D/A channel 1.

qWaveform Output Operation Mode

Waveform output operation mode is a particular and useful application of continuous output operation mode. In this mode, users can output the user-defined waveform pattern repetitively and continuously. Before this operation can begin, users have to use software to allocate the buffer memory and define the waveform pattern first. Then the host computer will transfer the waveform pattern from its buffer allocated in computer memory into the Output FIFO on the board, which in turn will transfer the waveform pattern to the DACs. When the trigger event occurs, each D/A channel running continuous output operation mode will output waveform pattern from FIFO in specific clock rate.

D/A Output Clock Sources

The PCI-1712 can adopt both internal and external clock sources for pacing the analog output of each channel:

wInternal D/A output clock with 16-bit Counter

wExternal D/A output clock that is connected to AO_CLK on the PCLD-8712 screw terminal board

The internal and external D/A output clocks are described in more detail as follows:

qInternal D/A Output Clock

The internal D/A output clock uses a 10 MHz time base. Conversions start on the rising edge of the counter output. Through software to specify the clock source as internal and the clock frequency to pace

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PCI-1712/1712L User’s Manual

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Contents MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Appendix D. Register Structure and Format Calibration100 Figures Auto A/D Calibration Dialog Box Corresponding Full Scale values for various Input I/O Connector Signal Description PartTable D-1PCI-1712/1712L register format Part Table D-2 Table D-3102 100101 Page Introduction FeaturesPlug-and-Play Function PCI-Bus Mastering Data TransferOn-board Fifo Memory Automatic Channel/Gain/SD*/BU* ScanningContinuous Analog Output Installation GuideOn-board Programmable Multifunction Counter/Timer Installation Flow Chart Wiring Boards AccessoriesWiring Cable Chapter Unpacking InstallationSetup Screen of Advantech Automation Software Driver InstallationDifferent options for Driver Setup Hardware InstallationChapter Device name listed on the Device Manager Setting Up the Device Device Setup & ConfigurationDevices Found dialog box Configuring the DeviceFor bipolar For unipolarTesting Analog Input Function Device TestingTesting Digital Input Function Testing Analog Output Function PCI-1712 onlyTesting Counter Function Testing Digital Output Function14 Digital output tab on the Device Test dialog box I/O Connector Signal ConnectionsOverview Pin AssignmentI/O connector pin assignments for the PCI-1712/1712L I/O Connector Signal Description Part Connector Signal DescriptionSignal Name Reference Direction Description Counter 0 Gate Input. This pin is for Differential Channel Connections Analog Input ConnectionsSingle-ended Channel Connections Chapter Differential input channel connection floating signal Source Analog output connections Analog Output ConnectionsField Wiring Considerations Programming Choices Software OverviewDLL Driver Register-level ProgrammingProgramming Tools DLL Driver Programming RoadmapProgramming with DLL Driver Function Library Troubleshooting DLL Driver ErrorChapter Principles of Operation Analog Input FeaturesAnalog Input Ranges and Gains Gains and Analog Input RangeAnalog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Sample Clock Sources Pre-Trigger Acquisition ModeTrigger Sources PCI-1712/1712L Sample Clock SourceAnalog Input Data Format Analog Input Data FormatAnalog Output Operation Modes Analog Output FeaturesAnalog Output Ranges Output Clock Sources Trigger Sources Analog Output Data Format Digital I/O FeaturesAnalog Output Data Format Clock sources Counter/Timer FeaturesGate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive VR Assignment CalibrationA/D Calibration D/A Calibration Selecting the device you want to calibrate Calibration UtilityAuto A/D Calibration Dialog Box Channel Auto-CalibrationA/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel 13 Selecting Input Rage in Manual A/D Calibration panel Channel Manual-Calibration14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Analog Input SpecificationDigital Input /Output Analog Output PCI-1712 onlyGeneral Counter/TimerAppendix a Block Diagram Block DiagramAppendix B Board Layout Screw-terminal BoardFigure C-2 CN2 pin assignments for the PCLD-8712 Pin AssignmentSingle-ended Connections Differential Connections I/O Port Address Map Register Structure and FormatTable D-1 PCI-1712/1712L register format Part Appendix DBase PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W Channel and A/D data Read Base + A/D Single Value Acquisition Write BASE+0Data of A/D Conversion CH2 to CH0 Channel NumberTable D-3 Register for A/D channel range setting A/D Channel Range Setting Write BASE+2Single-ended or Differential Bipolar or UnipolarTable D-4 Gain Codes for the PCI-1712/1712L MUX Control Write BASE+4Table D-5 Register for multiplexer control Start Scan Channel NumberAppendix D Table D-6 Register for A/D control/status Analog input acquisition mode registerA/D Control/Status Register Write/Read BASE+6 Trigger source control register Sample clock source select registerTrigger edge control register Analog I/O calibration bitAitrgf Analog input trigger flag Clear interrupt and Fifo Write BASE+8Table D-8 Register for clear interrupt and Fifo Clear A/D FifoInterrupt flag Interrupt and Fifo status Read BASE+8Fifo empty flag Fifo half-full flag10 D/A control/status register Write/Read BASE+A Channel 1 unipolar or bipolar output Table D-11 Analog output operation modeClock source select register Aotrgf Analog output trigger flagData 11 D/A Channel 0/1 Data Write BASE+C/ETable D-12 Register for D/A channel 0/1 data Table D-13 Register for 82C54 counter chip 12 82C54 Counter Chip 0 Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip 13 82C54 counter chip 1 Write/Read BASE+18 to 1ETable D-16 Table of Cn1 to Cn0 register Cn1 to Cn0 Counter clock source control register n = 0,1,2CQn Counter clock set register n = 0,1,2 CPn Counter clock edge control register n = 0,1,2Gn1 to Gn0 Counter gate source control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerGPn Counter gate polarity control register n = 0,1,2 GRn Pulse width measurement reset register n = 0,1,2GQn Counter gate set register n = 0,1,2 GATEn Gate status n = 0,1,2GATESn Pulse width measurement status bit n = 0,1,2 Digital I/O registers Write/Read BASE+28CLKSEL1 & 0 Counter internal clock select register DO15 to DO0 Digital output data registerCalibration command registers Write BASE+2C Digital I/O configuration registers Write/Read BASE+2ADIOC1 to DIOC0 Digital I/O configuration register DI15 to DI0 Digital input data registerD7 to D0 Calibration data CM3 to CM0 Calibration commandTable D-23 Calibration command DA11 to DA0 D/A data Table D-24 Register for D/A channel data

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