Konica Minolta PCI-1712L user manual Analog Input Data Format

Page 51

Chapter 5

the PCLD-8712 screw terminal board. The trigger signal is TTL- compatible.

qAnalog Threshold Trigger

For analog input operations, an analog trigger event occurs when the PCI-1712/1712L detects a transition from above a threshold level to below a threshold level (falling edge), or a transition from below a threshold level to above a threshold level (rising edge). User should connect analog signals from external device or internal analog output channel on board to external screw terminal ANA_TRG on the PCLD- 8712 screw terminal board.

On the PCI-1712/1712L, the threshold level is set using a dedicated 8- bit DAC; the hysteresis is fixed at 50 mV. Using software, you can program the threshold level by writing a voltage value to this DAC; this value can range from -10 V to +10 V.

Analog Input Data Format

Table 5-2: Analog Input Data Format

 

A/D code

Mapping Voltage

 

 

 

 

 

Hex.

 

Dec.

Unipolar

Bipolar

 

 

 

 

 

000h

 

0d

0

-FS/2

 

 

 

 

 

7FFh

 

2047d

FS/2 - 1 LSB

-1 LSB

 

 

 

 

 

800h

 

2048d

FS/2

0

 

 

 

 

 

FFFh

 

4095d

FS - 1 LSB

FS/2 - 1 LSB

 

 

 

 

 

 

1 LSB

FS/4096

FS/4096

 

 

 

 

 

Table 5-3: The corresponding Full Scale values for various Input

Voltage Ranges

Gain

Uniplar

 

Bipolar

 

 

 

 

 

 

 

Range

 

FS

Range

 

FS

 

 

 

 

 

 

 

 

 

 

0.5

N/A

 

N/A

± 10 V

 

20

 

 

 

 

 

 

 

1

0 ~ 10 V

 

10

± 5 V

 

10

 

 

 

 

 

 

 

2

0 ~ 5 V

 

5

± 2.5 V

 

5

 

 

 

 

 

 

 

4

0 ~ 2.5 V

 

2.5

± 1.25 V

 

2.5

 

 

 

 

 

 

 

8

0 ~ 1.25 V

 

1.25

± 0.625 V

 

1.25

 

 

 

 

 

 

 

Advantech Co., Ltd.

– 39 –

PCI-1712/1712L User’s Manual

www.advantech.com

 

 

Page 50 Page 52
Image 51
Page 50 Page 52
Contents MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Appendix D. Register Structure and Format Calibration100 Figures Auto A/D Calibration Dialog Box Table D-3 I/O Connector Signal Description PartCorresponding Full Scale values for various Input Table D-1PCI-1712/1712L register format Part Table D-2100 101102 Page Introduction FeaturesAutomatic Channel/Gain/SD*/BU* Scanning PCI-Bus Mastering Data TransferPlug-and-Play Function On-board Fifo MemoryInstallation Guide On-board Programmable Multifunction Counter/TimerContinuous Analog Output Installation Flow Chart Accessories Wiring CableWiring Boards Chapter Unpacking InstallationSetup Screen of Advantech Automation Software Driver InstallationDifferent options for Driver Setup Hardware InstallationChapter Device name listed on the Device Manager Setting Up the Device Device Setup & ConfigurationDevices Found dialog box Configuring the DeviceFor bipolar For unipolarTesting Analog Input Function Device TestingTesting Digital Input Function Testing Analog Output Function PCI-1712 onlyTesting Counter Function Testing Digital Output Function14 Digital output tab on the Device Test dialog box Pin Assignment Signal ConnectionsI/O Connector OverviewI/O connector pin assignments for the PCI-1712/1712L I/O Connector Signal Description Part Connector Signal DescriptionSignal Name Reference Direction Description Counter 0 Gate Input. This pin is for Analog Input Connections Single-ended Channel ConnectionsDifferential Channel Connections Chapter Differential input channel connection floating signal Source Analog output connections Analog Output ConnectionsField Wiring Considerations Register-level Programming Software OverviewProgramming Choices DLL DriverProgramming Tools DLL Driver Programming RoadmapProgramming with DLL Driver Function Library Troubleshooting DLL Driver ErrorChapter Gains and Analog Input Range Analog Input FeaturesPrinciples of Operation Analog Input Ranges and GainsAnalog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Sample Clock Sources Pre-Trigger Acquisition ModeTrigger Sources PCI-1712/1712L Sample Clock SourceAnalog Input Data Format Analog Input Data FormatAnalog Output Features Analog Output RangesAnalog Output Operation Modes Output Clock Sources Trigger Sources Digital I/O Features Analog Output Data FormatAnalog Output Data Format Clock sources Counter/Timer FeaturesGate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive VR Assignment CalibrationA/D Calibration D/A Calibration Selecting the device you want to calibrate Calibration UtilityAuto A/D Calibration Dialog Box Channel Auto-CalibrationA/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel 13 Selecting Input Rage in Manual A/D Calibration panel Channel Manual-Calibration14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Analog Input SpecificationDigital Input /Output Analog Output PCI-1712 onlyGeneral Counter/TimerAppendix a Block Diagram Block DiagramAppendix B Board Layout Screw-terminal BoardFigure C-2 CN2 pin assignments for the PCLD-8712 Pin AssignmentSingle-ended Connections Differential Connections I/O Port Address Map Register Structure and FormatTable D-1 PCI-1712/1712L register format Part Appendix DBase PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W CH2 to CH0 Channel Number A/D Single Value Acquisition Write BASE+0Channel and A/D data Read Base + Data of A/D ConversionBipolar or Unipolar A/D Channel Range Setting Write BASE+2Table D-3 Register for A/D channel range setting Single-ended or DifferentialStart Scan Channel Number MUX Control Write BASE+4Table D-4 Gain Codes for the PCI-1712/1712L Table D-5 Register for multiplexer controlAppendix D Analog input acquisition mode register A/D Control/Status Register Write/Read BASE+6Table D-6 Register for A/D control/status Analog I/O calibration bit Sample clock source select registerTrigger source control register Trigger edge control registerClear A/D Fifo Clear interrupt and Fifo Write BASE+8Aitrgf Analog input trigger flag Table D-8 Register for clear interrupt and FifoFifo half-full flag Interrupt and Fifo status Read BASE+8Interrupt flag Fifo empty flag10 D/A control/status register Write/Read BASE+A Aotrgf Analog output trigger flag Table D-11 Analog output operation modeChannel 1 unipolar or bipolar output Clock source select register11 D/A Channel 0/1 Data Write BASE+C/E Table D-12 Register for D/A channel 0/1 dataData Table D-13 Register for 82C54 counter chip 12 82C54 Counter Chip 0 Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip 13 82C54 counter chip 1 Write/Read BASE+18 to 1ETable D-16 Table of Cn1 to Cn0 register Cn1 to Cn0 Counter clock source control register n = 0,1,2Table D-17 Table of Gn1 to Gn0 register CPn Counter clock edge control register n = 0,1,2CQn Counter clock set register n = 0,1,2 Gn1 to Gn0 Counter gate source control register n = 0,1,2GATEn Gate status n = 0,1,2 GRn Pulse width measurement reset register n = 0,1,2GPn Counter gate polarity control register n = 0,1,2 GQn Counter gate set register n = 0,1,2DO15 to DO0 Digital output data register Digital I/O registers Write/Read BASE+28GATESn Pulse width measurement status bit n = 0,1,2 CLKSEL1 & 0 Counter internal clock select registerDI15 to DI0 Digital input data register Digital I/O configuration registers Write/Read BASE+2ACalibration command registers Write BASE+2C DIOC1 to DIOC0 Digital I/O configuration registerCM3 to CM0 Calibration command Table D-23 Calibration commandD7 to D0 Calibration data DA11 to DA0 D/A data Table D-24 Register for D/A channel data

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