Konica Minolta PCI-1712L MUX Control Write BASE+4, Table D-4 Gain Codes for the PCI-1712/1712L

Page 97

 

 

 

 

 

 

APPENDIX D

 

Table D-4: Gain Codes for the PCI-1712/1712L

 

 

 

 

 

 

 

 

B/U

 

Gain Code

 

Gain

Input Range (V)

 

 

 

 

 

G2

G1

G0

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

1

-5

~ +5

 

 

 

 

 

 

 

 

 

0

0

0

1

2

-2.5

~ +2.5

 

 

 

 

 

 

 

 

 

0

0

1

0

4

-1.25

~ +1.25

 

 

 

 

 

 

 

 

 

0

0

1

1

8

-0.625

~ +0.625

 

 

 

 

 

 

 

 

0

1

0

0

0.5

-10 ~ +10

 

 

 

 

 

 

 

 

1

0

0

0

1

0 ~ 10

 

 

 

 

 

 

 

 

1

0

0

1

2

0 ~ 5

 

 

 

 

 

 

 

 

1

0

1

0

4

0 ~ 2.5

 

 

 

 

 

 

 

 

1

0

1

1

8

0 ~ 1.25

 

 

 

 

 

 

 

 

 

D.6 MUX Control — Write BASE+4

Table D-5: Register for multiplexer control

Base Add.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

W

 

 

 

 

 

 

Multiplexer setting

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STP3

STP2

STP1

STP0

 

 

 

 

STR3

STR2

STR1

STR0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STR3 ~ STR0

 

Start Scan Channel Number

 

 

 

 

STP3 ~ STP0

 

Stop Scan Channel Number

 

 

 

 

When you set the gain code of analog input channel n, you should set the MUX start & stop channel number to channel n to prevent any unexpected errors. In fact, Write BASE+4 bit 3 to 0, STR3 ~ STR0, act as a pointer to the address of channel n in the SRAM when you program the A/D channel setting (refer to Section D.5).

Note:

✎We recommend that you set the same start and stop channel when writing to the register Write BASE+2. Otherwise, if the A/D trigger source is on, the multiplexer will continuously scan between channels and the range settings may be set to an unexpected channel. Make sure the A/D trigger source is turned off to avoid this kind of error.

Advantech Co., Ltd.

– 85 –

PCI-1712/1712L User’s Manual

www.advantech.com

 

 

Page 96 Page 98
Image 97
Page 96 Page 98
Contents MS/s, 12-bit, 16-ch High- Speed Multifunction Card PCI-1712/1712L Quick Start Unpacking Device Installation Page Contents Appendix D. Register Structure and Format Calibration100 Figures Auto A/D Calibration Dialog Box Corresponding Full Scale values for various Input I/O Connector Signal Description PartTable D-1PCI-1712/1712L register format Part Table D-2 Table D-3101 100102 Page Introduction FeaturesPlug-and-Play Function PCI-Bus Mastering Data TransferOn-board Fifo Memory Automatic Channel/Gain/SD*/BU* ScanningOn-board Programmable Multifunction Counter/Timer Installation GuideContinuous Analog Output Installation Flow Chart Wiring Cable AccessoriesWiring Boards Chapter Unpacking InstallationSetup Screen of Advantech Automation Software Driver InstallationDifferent options for Driver Setup Hardware InstallationChapter Device name listed on the Device Manager Setting Up the Device Device Setup & ConfigurationDevices Found dialog box Configuring the DeviceFor bipolar For unipolarTesting Analog Input Function Device TestingTesting Digital Input Function Testing Analog Output Function PCI-1712 onlyTesting Counter Function Testing Digital Output Function14 Digital output tab on the Device Test dialog box I/O Connector Signal ConnectionsOverview Pin AssignmentI/O connector pin assignments for the PCI-1712/1712L I/O Connector Signal Description Part Connector Signal DescriptionSignal Name Reference Direction Description Counter 0 Gate Input. This pin is for Single-ended Channel Connections Analog Input ConnectionsDifferential Channel Connections Chapter Differential input channel connection floating signal Source Analog output connections Analog Output ConnectionsField Wiring Considerations Programming Choices Software OverviewDLL Driver Register-level ProgrammingProgramming Tools DLL Driver Programming RoadmapProgramming with DLL Driver Function Library Troubleshooting DLL Driver ErrorChapter Principles of Operation Analog Input FeaturesAnalog Input Ranges and Gains Gains and Analog Input RangeAnalog Input Acquisition Modes Post-Trigger Acquisition Mode About-Trigger Acquisition Mode Sample Clock Sources Pre-Trigger Acquisition ModeTrigger Sources PCI-1712/1712L Sample Clock SourceAnalog Input Data Format Analog Input Data FormatAnalog Output Ranges Analog Output FeaturesAnalog Output Operation Modes Output Clock Sources Trigger Sources Analog Output Data Format Digital I/O FeaturesAnalog Output Data Format Clock sources Counter/Timer FeaturesGate Types and Sources Counter/timer operation modes Chapter Chapter Frequency measurement Chapter Chapter Pulse width measurement Internal, and gate use for pulse Show the duty ratio of positive VR Assignment CalibrationA/D Calibration D/A Calibration Selecting the device you want to calibrate Calibration UtilityAuto A/D Calibration Dialog Box Channel Auto-CalibrationA/D Calibration Procedure A/D Calibration is finished Range Selection in D/A Calibration 11 Calibrating D/A Channel 13 Selecting Input Rage in Manual A/D Calibration panel Channel Manual-Calibration14 Adjusting registers 15 & -16 Selecting D/A Range Choosing Output Voltage 17 Adjusting registers Chapter Analog Input SpecificationDigital Input /Output Analog Output PCI-1712 onlyGeneral Counter/TimerAppendix a Block Diagram Block DiagramAppendix B Board Layout Screw-terminal BoardFigure C-2 CN2 pin assignments for the PCLD-8712 Pin AssignmentSingle-ended Connections Differential Connections I/O Port Address Map Register Structure and FormatTable D-1 PCI-1712/1712L register format Part Appendix DBase PCI-1712/1712L Register Format Address Channel data for continuous output operation mode 30 W Channel and A/D data Read Base + A/D Single Value Acquisition Write BASE+0Data of A/D Conversion CH2 to CH0 Channel NumberTable D-3 Register for A/D channel range setting A/D Channel Range Setting Write BASE+2Single-ended or Differential Bipolar or UnipolarTable D-4 Gain Codes for the PCI-1712/1712L MUX Control Write BASE+4Table D-5 Register for multiplexer control Start Scan Channel NumberAppendix D A/D Control/Status Register Write/Read BASE+6 Analog input acquisition mode registerTable D-6 Register for A/D control/status Trigger source control register Sample clock source select registerTrigger edge control register Analog I/O calibration bitAitrgf Analog input trigger flag Clear interrupt and Fifo Write BASE+8Table D-8 Register for clear interrupt and Fifo Clear A/D FifoInterrupt flag Interrupt and Fifo status Read BASE+8Fifo empty flag Fifo half-full flag10 D/A control/status register Write/Read BASE+A Channel 1 unipolar or bipolar output Table D-11 Analog output operation modeClock source select register Aotrgf Analog output trigger flagTable D-12 Register for D/A channel 0/1 data 11 D/A Channel 0/1 Data Write BASE+C/EData Table D-13 Register for 82C54 counter chip 12 82C54 Counter Chip 0 Write/Read BASE+10 toTable D-14 Register for 82C54 counter chip 13 82C54 counter chip 1 Write/Read BASE+18 to 1ETable D-16 Table of Cn1 to Cn0 register Cn1 to Cn0 Counter clock source control register n = 0,1,2CQn Counter clock set register n = 0,1,2 CPn Counter clock edge control register n = 0,1,2Gn1 to Gn0 Counter gate source control register n = 0,1,2 Table D-17 Table of Gn1 to Gn0 registerGPn Counter gate polarity control register n = 0,1,2 GRn Pulse width measurement reset register n = 0,1,2GQn Counter gate set register n = 0,1,2 GATEn Gate status n = 0,1,2GATESn Pulse width measurement status bit n = 0,1,2 Digital I/O registers Write/Read BASE+28CLKSEL1 & 0 Counter internal clock select register DO15 to DO0 Digital output data registerCalibration command registers Write BASE+2C Digital I/O configuration registers Write/Read BASE+2ADIOC1 to DIOC0 Digital I/O configuration register DI15 to DI0 Digital input data registerTable D-23 Calibration command CM3 to CM0 Calibration commandD7 to D0 Calibration data DA11 to DA0 D/A data Table D-24 Register for D/A channel data

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