Intel Core 2, Intel Core2 Duo Processor and Mobile Intel GME965 Express Chipset user manual Atx

Page 36

 

 

 

 

Theory of Operation

 

 

 

 

 

 

Component

Voltage

Supply

Rail

 

Reference

/ Interface

Plane

 

 

 

Designator

 

 

 

 

 

 

System

ATX

+V5A

+V5_ATX

 

R4J1*

 

 

 

 

 

 

System

ATX

+V3.3A

+V3.3_ATX

 

R4W23*

 

 

 

 

 

 

System

ATX

+V12_ATX

+VBATA

 

R4Y1

 

 

 

 

 

 

System

ATX

-V12_ATX

-V12A

 

R4Y2

 

 

 

 

 

 

System

ATX

+V5SB_ATX

+V5SB_ATXA

 

R5H17

 

 

 

 

 

 

System

+VAC_B

+VAC_BRCK_IN

NEG_SENSE

 

R1G8

 

RCK

 

 

 

 

 

 

 

 

 

 

§

36

316704-001 / Development Kit User’s Manual

Image 36
Contents June 316704-001 / Development Kit User’s Manual Contents Figures TablesDocument Revision Description Revision Date Initial public release JuneContent Overview Text ConventionsText Conventions Notation DefinitionGlossary of Terms and Acronyms Terms and AcronymsTerm/Acronym Definition Experience under all conditions Acronyms Acronym DefinitionBios LOM Support Options Product LiteratureElectronic Support Systems Additional Technical Support Intel Literature CentersRelated Documents Related DocumentsDocument Title Location Development Board Features Development Board feature Set SummaryOverview Development Board Comments ImplementationUSB Software Key Features Included Hardware and DocumentationAMI Bios Before You BeginGetting Started Setting Up the Development Board Configuring the Bios Block Diagram Mechanical Form FactorSystem Features and Operation Thermal ManagementMobile Intel GME965 Gmch System Memory 1.2 DMIAdvanced Graphics and Display Interfaces 2 ICH8-M PCI Express x16 SlotPCI Express* Slots PCI SlotsUSB Connectors On-Board LANHigh Definition Audio 2.5 ATA/ StorageBios Firmware Hub FWH LPC Super I/O SIO/LPC SlotSerial, IrDA 2.10 SPIBios Location Strapping Options System Management Controller SMC/Keyboard ControllerClocks Real Time ClockPower Management States Power Management StatesClock Generation Post Code DebuggerPower Management M-States Description Main Memory StateSubsystem1 Manageability Subsystem2Power Measurement Support Sleep Signals and M-State DefinitionSignal Development Board Voltage Rails Component Voltage Supply Rail Reference LAN +V3.3MLANSW VDDCK505 ATX Primary Features Development Board Component LocationsDevelopment Board Component Location Legend Reference FunctionBack Panel Connectors J8D1TV-Out D-Connector Description Ref DesConfiguration Settings Connector to Component Video CableReference Function Default Setting Optional Setting For each VID signal J7J2 Power On and Reset Buttons NMILEDs Function ReferenceOther Headers, Slots and Sockets 1 H8 Programming HeadersExpansion Slots and Sockets Expansion Slots and SocketsReference Slot/Socket Description Detail Designator 2.1 478 Pin Grid Array Micro-FCPGA Socket PCI ExpressPCI Express* x16 Pinout J6B2 Reference Slot/Socket Description DetailPERST# PRSNT#2 2.3 ADD2/Media Expansion Card MEC Slot ADD2 Slot J6B2End of x1 Connector A19 Reserved B19 SDVOGreen+ A20 A50 Reserved B50 A51 MEC Slot J6B2 SDVOCCLK+ PCI Express* x1 Pinout J6B1, J7B1, J8B4 IDE Connector IDE ConnectorPin Signal Fan Connectors Sata Port 0 ‘Direct Connect’ Connector Pinout J8J1Sata Power Connection J7H2 Sata PinoutFan Connectors J2B3, J2C1 Fan Connector J2F1Front Panel Connector Pin Signal DefinitionUSB Headers J6H3, J6H4 USB HeadersAppendix a . Heatsink Installation Instructions Backplate Pins Applying the Thermal Grease Installing the Heatsink Plugging in the Fan