Intel Intel Core2 Duo Processor and Mobile Intel GME965 Express Chipset, Core 2 On-Board LAN

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Theory of Operation

3.4.2.3On-Board LAN

The development board has one RJ-45 interface – at connector J5A1 - through which 10/100/1000 ethernet is available. The ethernet MAC is located in the ICH8-M and the PHY is located externally in the 82566MM LAN Connect Interface (LCI) device. The 82566MM is connected to the ICH8-M via two interfaces: LCI for 10/100 Mbps traffic and GLCI (Gigabit LCI) for 1000Mbps traffic. Intel® Active Management Technology is optionally supported through these components.

Information on Intel® Active Management Technology can be found at:

http://www.intel.com/technology/manage/iamt/

Note: Further details on the location of the RJ-45 interface can be found in Section 4.2.

3.4.2.4High Definition Audio

Intel® High Definition Audio is not supported on the development board.

3.4.2.5ATA/ Storage

The development board has one parallel ATA IDE connector and three serial ATA connectors.

The parallel ATA IDE Connector is a standard 40-pin connector at J7J4. This connector supports up to two Ultra ATA/100 hard drives; one master and one slave.

There are three SATA connectors on the development board – one ‘Direct Connect’ connector and two ‘Cable Connect’ connectors. The ‘Direct Connect’ connector, located at J8J1, provides both signaling and power while the ‘Cable Connect’ connectors, located at J7H1 and J7J3, only provides signals (the user typically uses an ATX power supply for the drive power). A green LED at location CR6J1 indicates activity on the ATA channel.

The development board also supports ‘ATA swap’ capability for both the parallel IDE channel and the serial ATA channels. A device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. The parallel IDE device should be powered from the power connector, J4J2, on the development board to utilize the hot swap feature. This feature requires customer- developed software support.

Note: Desktop hard drives must be powered using the external ATX power supply, not the onboard power supply.

The Mobile Intel® GME965 Express Chipset includes Intel® Matrix Storage Technology, providing greater performance and reliability through features such as Native Command Queuing (NCQ) and RAID 0/1. For more information about Intel® Matrix Storage Technology, refer to Intel’s website at:

http://www.intel.com/design/chipsets/matrixstorage_sb.htm

3.4.2.6USB Connectors

The ICH8-M provides a total of ten USB 2.0 ports. Three ports are routed to a triple- stack USB connector at J3A1. Two ports are routed to a combination RJ-45/dual USB

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316704-001 / Development Kit User’s Manual

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Contents June 316704-001 / Development Kit User’s Manual Contents Figures TablesDocument Revision Description Revision Date Initial public release JuneContent Overview Text ConventionsText Conventions Notation DefinitionTerm/Acronym Definition Glossary of Terms and AcronymsTerms and Acronyms Experience under all conditions Acronyms Acronym DefinitionBios LOM Electronic Support Systems Additional Technical Support Support OptionsProduct Literature Intel Literature CentersDocument Title Location Related DocumentsRelated Documents Overview Development Board FeaturesDevelopment Board feature Set Summary Development Board Comments ImplementationUSB Software Key Features Included Hardware and DocumentationAMI Bios Before You BeginGetting Started Setting Up the Development Board Configuring the Bios Block Diagram Mechanical Form FactorMobile Intel GME965 Gmch System Features and OperationThermal Management Advanced Graphics and Display Interfaces System Memory1.2 DMI PCI Express* Slots 2 ICH8-MPCI Express x16 Slot PCI SlotsHigh Definition Audio USB ConnectorsOn-Board LAN 2.5 ATA/ StorageSerial, IrDA Bios Firmware Hub FWHLPC Super I/O SIO/LPC Slot 2.10 SPIClocks Bios Location Strapping OptionsSystem Management Controller SMC/Keyboard Controller Real Time ClockClock Generation Power Management StatesPower Management States Post Code DebuggerSubsystem1 Power Management M-StatesDescription Main Memory State Manageability Subsystem2Signal Power Measurement SupportSleep Signals and M-State Definition Development Board Voltage Rails Component Voltage Supply Rail Reference LAN +V3.3MLANSW VDDCK505 ATX Primary Features Development Board Component LocationsDevelopment Board Component Location Legend Reference FunctionBack Panel Connectors J8D1TV-Out D-Connector Description Ref DesConfiguration Settings Connector to Component Video CableReference Function Default Setting Optional Setting For each VID signal J7J2 Power On and Reset Buttons NMILEDs Function ReferenceOther Headers, Slots and Sockets 1 H8 Programming HeadersReference Slot/Socket Description Detail Designator Expansion Slots and SocketsExpansion Slots and Sockets PCI Express* x16 Pinout J6B2 2.1 478 Pin Grid Array Micro-FCPGA SocketPCI Express Reference Slot/Socket Description DetailPERST# PRSNT#2 2.3 ADD2/Media Expansion Card MEC Slot ADD2 Slot J6B2End of x1 Connector A19 Reserved B19 SDVOGreen+ A20 A50 Reserved B50 A51 MEC Slot J6B2 SDVOCCLK+ PCI Express* x1 Pinout J6B1, J7B1, J8B4 Pin Signal IDE ConnectorIDE Connector Sata Power Connection J7H2 Fan ConnectorsSata Port 0 ‘Direct Connect’ Connector Pinout J8J1 Sata PinoutFront Panel Connector Fan Connectors J2B3, J2C1Fan Connector J2F1 Pin Signal DefinitionUSB Headers J6H3, J6H4 USB HeadersAppendix a . Heatsink Installation Instructions Backplate Pins Applying the Thermal Grease Installing the Heatsink Plugging in the Fan