Intel GME965, Core 2 user manual USB Headers J6H3, J6H4

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Hardware Reference

16

+V5

5 volt supply

4.6.2.9USB Headers (J6H3, J6H4)

The USB headers implement 4 additional USB ports on the development board. Connector J6H3 implements ports 7 and 8 and connector J6H4 implements ports 2 and 4.

Table 29. USB Headers

Pin

Signal

Definition

1

+V5A_L_USBPWR

5 volt – Always On

 

 

 

2

+V5A_L_USBPWR

5 volt – Always On

 

 

 

3

USB_PNx

Data- (USB Port x)

 

 

 

4

USB_PNy

Data- (USB Port y)

 

 

 

5

USB_PPx

Data+ (USB Port x)

 

 

 

6

USB_PPy

Data+ (USB Port y)

 

 

 

7

GND

Ground

 

 

 

8

GND

Ground

 

 

 

9

N/C

No Connect

 

 

 

10

N/C

No Connect

 

 

 

§

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Contents June 316704-001 / Development Kit User’s Manual Contents Tables FiguresInitial public release June Document Revision Description Revision DateText Conventions Content OverviewNotation Definition Text ConventionsTerms and Acronyms Glossary of Terms and AcronymsTerm/Acronym Definition Experience under all conditions Acronym Definition AcronymsBios LOM Product Literature Support OptionsElectronic Support Systems Additional Technical Support Intel Literature CentersRelated Documents Related DocumentsDocument Title Location Development Board feature Set Summary Development Board FeaturesOverview Development Board Comments ImplementationUSB Included Hardware and Documentation Software Key FeaturesBefore You Begin AMI BiosGetting Started Setting Up the Development Board Configuring the Bios Mechanical Form Factor Block DiagramThermal Management System Features and OperationMobile Intel GME965 Gmch 1.2 DMI System MemoryAdvanced Graphics and Display Interfaces PCI Express x16 Slot 2 ICH8-MPCI Express* Slots PCI SlotsOn-Board LAN USB ConnectorsHigh Definition Audio 2.5 ATA/ StorageLPC Super I/O SIO/LPC Slot Bios Firmware Hub FWHSerial, IrDA 2.10 SPISystem Management Controller SMC/Keyboard Controller Bios Location Strapping OptionsClocks Real Time ClockPower Management States Power Management StatesClock Generation Post Code DebuggerDescription Main Memory State Power Management M-StatesSubsystem1 Manageability Subsystem2Sleep Signals and M-State Definition Power Measurement SupportSignal Development Board Voltage Rails Component Voltage Supply Rail Reference LAN +V3.3MLANSW VDDCK505 ATX Development Board Component Locations Primary FeaturesReference Function Development Board Component Location LegendJ8D1 Back Panel ConnectorsDescription Ref Des TV-Out D-ConnectorConnector to Component Video Cable Configuration SettingsReference Function Default Setting Optional Setting For each VID signal J7J2 NMI Power On and Reset ButtonsFunction Reference LEDs1 H8 Programming Headers Other Headers, Slots and SocketsExpansion Slots and Sockets Expansion Slots and SocketsReference Slot/Socket Description Detail Designator PCI Express 2.1 478 Pin Grid Array Micro-FCPGA SocketPCI Express* x16 Pinout J6B2 Reference Slot/Socket Description DetailPERST# PRSNT#2 ADD2 Slot J6B2 2.3 ADD2/Media Expansion Card MEC SlotEnd of x1 Connector A19 Reserved B19 SDVOGreen+ A20 A50 Reserved B50 A51 MEC Slot J6B2 SDVOCCLK+ PCI Express* x1 Pinout J6B1, J7B1, J8B4 IDE Connector IDE ConnectorPin Signal Sata Port 0 ‘Direct Connect’ Connector Pinout J8J1 Fan ConnectorsSata Power Connection J7H2 Sata PinoutFan Connector J2F1 Fan Connectors J2B3, J2C1Front Panel Connector Pin Signal DefinitionUSB Headers USB Headers J6H3, J6H4Appendix a . Heatsink Installation Instructions Backplate Pins Applying the Thermal Grease Installing the Heatsink Plugging in the Fan