Intel 80C186EB, 80L188EC, 80L186EB, 80L186EC, 80C188EB, 80L188EB, 80C188EC, 80C186EC Step Sstep

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iECM-86 COMMANDS

Super-stepping is similar to stepping, except that the super-step command treats an interrupt service routine or a subroutine call (and the body of the subroutine that is called) as one indivisible instruction. This allows the user to ignore the details of subroutines and interrupt service routines while evaluating code. This may allow limited stepping through code while operating in a concurrent environment, but the system will not operate in real time. A better approach is to use the GO command to execute to a specified breakpoint and then step through the code being tested, looking for proper operation.

iECM-86 implements the step operation by using the trap flag (TF). To step over a given instruction, iECM-86 sets the trap flag to put the processor into single-step mode. In this mode, the CPU automatically generates an internal interrupt after each instruction, allowing a program to be inspected as it executes. After the processor receives this trap interrupt, it restores all of the user flags overwritten by the iECM flags.

Super-stepping is also accomplished by setting the trap flag, except for CALL instructions, which are treated as a special case. During a STEP, the iECM-86 sets the trap flag; during a super-step an INT3 is placed at the instruction following the CALL. Interrupts are suppressed during STEP operations by saving the user’s IF bit, clearing it before the STEP occurs, and then restoring it. During a GO or SSTEP command, all instructions are executed by the target.

The iECM-86 commands that implement step operations are the following:

STEP

STEP count

STEP FROM code_addr

STEP FROM code_addr count

SSTEP

SSTEP count

SSTEP FROM code_addr

SSTEP FROM code_addr count

Aside from the style of the actual step operation, the SSTEP and STEP commands behave the same. They are called single-stepping commands are described as follows.

{STEP SSTEP}

This command single-steps one time.

{STEP SSTEP} count This command single-steps count times.

{STEP SSTEP} FROM code_addr

This command loads the user's program counter (PC) with code_addr and then single-steps one time.

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Contents Intel 186 EB/EC Evaluation Board User’s Manual Copyright Intel Corporation Contents Contents Chapter Introduction to the Software Trapisr Rism CommandsIrism Variables Rism StructureFigures About This Manual Page Chapter About this Manual Content OverviewItalics Notation ConventionsDocument Name Intel Order # Related DocumentsWorld Wide Web FaxBack ServiceElectronic Support Systems Customer Support Telephone Numbers Technical SupportPage Getting Started Page Getting Started Intel 186 EC Evaluation Board Layout WHAT’S in Your KIT System RequirementsIntel 186 EB/EC Evaluation Board USER’S Manual ECM86 Page Hardware Overview Page LA19/WRT Prot Jumper SummaryPackaging MicroprocessorLCD I/O Memory ConfigurationSram F000FFFFPhysical Memory Map Flash Program Memory Jumper Assembly for Flash Downloading Programmable Logic Sram Static MemoryE1 Jumper Power SupplyInit Serial InterfaceCTS P2 Serial ChannelPin to 9-Pin Adaptor Expansion Interface EC Peripheral Expansion Connector JP2 40 pinEB Peripheral Expansion Connector JP2 24 pin CPU Bus Expansion EB and EC LCD Interface Demo LCD InterfacePage Introduction to Software Page Introduction to the Software Software FeaturesEmbedded Controller Monitor ECM RestrictionsUser Interface Diag COM2, -COM1Quit POLL, -SIGNALReset SYSTEM, RES SYSTEM, RESET, RES 6 DOSReserved I/O Related InformationReserved Functions Reserved MemoryIECM-86 Commands Page Entering Commands Loading and Saving Object Code File OperationsInclude filename Other File OperationsLOG filename List filenameBreakpoints Resetting the TargetProgram Control BR bpnumber = codeaddr BR bpnumberGO Forever Program ExecutionProgram Stepping GO from codeaddr Till codeaddrGO from codeaddr Till codeaddr or codeaddr GO Till codeaddr or codeaddrStep Sstep Supported Data Types Displaying and Modifying Program VariablesByte byteaddress to byteaddress Byte CommandsByte byteaddress = bytevalue Word wordaddress to wordaddress Word CommandsByte byteaddress to byteaddress = bytevalue Word wordaddress = wordvalueDword dwordaddress = dwordvalue Dword CommandsWord wordaddress to wordaddress = wordvalue Dword dwordaddressStack stackaddress to stackaddress Stack CommandsDword dwordaddress to dwordaddress = dwordvalue Stack stackaddressPort portaddress = bytevalue String CommandsPort Commands String byteaddressWport wportaddress Wport CommandsPort portaddress to portaddress = bytevalue Processor Variables Wport wportaddress = wordvalueWport wportaddress to wportaddress Wport wportaddress to wportaddress = wordvaluePC =codeaddress IRISM-186 Commands Page Other Variables IRISM VariablesSending Data to the Host Rism CommandsRism Structure Receiving Data from the HostReadword Code 05H Setdataflag Code 00HTransmit Code 02H Readbyte Code 04HWritepc Code 11H Writedouble Code 09HLoadaddress Code 0AH Readpc Code 10HReadbport Code 16H TrapisrReportstatus Code 14H Monitorescape Code 15HWritereg Code 1CH Writewport Code 19HStep Code 1AH Readreg Code 1BHStart Up Commands / or \ Page Parts List Page PIN PWR Conn CN2PMLX PIN Header JUMP3PIN Header JUMP4 30 Header HDR2X30 ResetPIN SIP SKT SIP14 JP1SO20W XU9SOP44 Intel20 Header HDR2X20 Intel # PA28F400BV PNP Transistor SOT23 SMT PNP MMBT2907ALT1Table A-2 EC Board Manual Parts List Sheet 3 Index Index-2

80L188EB, 80C188EC, 80C188EB, 80L186EB, 80C186EB specifications

The Intel 80L188EC, 80C186EC, 80L186EC, 80C186EB, and 80L186EB microprocessors represent a significant evolution in Intel's 16-bit architecture, serving various applications in embedded systems and computing during the late 1980s and early 1990s. These microprocessors are designed to offer a blend of performance, efficiency, and versatility, making them suitable for a range of environments, including industrial control, telecommunications, and personal computing.

The Intel 80L188EC is a member of the 186 family, notable for its low-power consumption and integrated support for a range of peripheral devices. It operates at clock speeds of up to 10 MHz and features a 16-bit architecture, providing a balance of processing power and energy efficiency. The 80C186EC, on the other hand, is a more advanced version, offering enhanced performance metrics with faster clock speeds and improved processing capabilities, making it ideal for applications that require more computational power.

The 80L186EC shares similarities with the 80L188EC but is enhanced further for various low-power applications, especially where battery life is crucial. With a maximum clock speed of 16 MHz, it excels in scenarios demanding energy-efficient processing without sacrificing performance.

In contrast, the 80C186EB and 80L186EB are optimized versions that bring additional features to the table. The 80C186EB operates at higher clock speeds, coupled with an extended instruction set, enabling it to handle more complex tasks and run sophisticated software. These enhancements allow it to serve well in environments that require reliable performance under load, such as data acquisition systems or advanced control systems.

The 80L186EB is tailored for specific low-power scenarios, integrating Intel's sophisticated low-power technologies without compromising on speed. Utilizing advanced process technologies, these chips benefit from reduced heat output and extended operating life, a significant advantage in embedded applications.

Overall, these microprocessors showcase Intel's commitment to innovation in 16-bit processing, marked by their varying capabilities and power profiles tailored to meet the demands of diverse applications, from industrial systems to consumer electronics. Their legacy continues to influence subsequent generations of microprocessor designs, emphasizing performance, energy efficiency, and versatile applications in computing technology. As such, the Intel 80C186 and 80L188 families play a crucial role in understanding the evolution of microprocessor technology.
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