Philips ISP1301 manual Hardware description, Block diagram, Functional description

Philips Semiconductors ISP1301 USB OTG Transceiver Eval Kit User’s Guide

6. Hardware description

6.1.Block diagram

Figure 6-1 shows the block diagram of the ISP1301 evaluation board.

PARALLEL	PC PARALLEL-TO-I2C		4-PIN I2C
	CONVERTER		HEADER
				AUDIO INTERFACE
				(L/R SPEAKER LINE IN,
				MIC PRE-AMP OUT)
		INT)
ISA	PCF8584 I2C-BUS	(SCL, SDA, ADR,		DP, DM, ID
	CONTROLLER
		I2C-BUS		DP, DM, ID, VBUS
			ISP1301
			OTG TRANSCEIVER
				BUS
				V
				mini-AB Receptacle
	HC, DC and OTG CORE
FPGA	LOGIC INTERFACE
	CONNECTOR
INTERFACE		CORE INTERFACE (OE, VP, VM, RCV,
	(to the ISP1362 FPGA or
	Phone FPGA)	SPEED, SUSPEND, RESET, VDD_LGC)	VBAT	POW ER MANAGER
				ext
				V

Figure 6-1: Block diagram of the ISP1301 evaluation board

6.2.Functional description

A brief description of each function module is given in the following sections.

6.2.1.PCF8584 I2C-bus controller

This block provides functions of the I2C-bus to the 8-bit parallel-bus converter. It can connect to the Philips ISP1362 or ISP1161x ISA interface board, or any other generic 8-bit microprocessor interface through a 40-wire IDE cable. The PC or other microprocessor can service the interrupt from the ISP1301 and access the registers of the ISP1301 through this interface.

6.2.2.PC parallel to I2C converter

This interface provides an alternative method to access the ISP1301 I2C interface through the PC. The PC needs to emulate software I2C master to access the ISP1301 I2C slave.

6.2.3.HC, DC and OTG core logic interface connector

This interface provides connection to a Host Controller (HC), Device Controller (DC) or On-The-Go (OTG) core logic. This interface is used during OTG system-level evaluation or during compliance testing.

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User’s Guide	Rev. 1.0—February 2003	12 of 18