Purpose of the Peripheral | Texas Instruments TMS320C6452 DSP

User's Guide

SPRUF85 – October 2007

DSP DDR2 Memory Controller

1Introduction

This document describes the DDR2 memory controller in the device.

1.1Purpose of the Peripheral

The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage.

1.2Features

The DDR2 memory controller supports the following features:

∙JESD79D-2A standard compliant DDR2 SDRAM

∙256 Mbyte memory space

∙Data bus width of 32 or 16 bits

∙CAS latencies: 2, 3, 4, and 5

∙Internal banks: 1, 2, 4, and 8

∙Burst length: 8

∙Burst type: sequential

∙1 CE signal

∙Page sizes: 256, 512, 1024, and 2048

∙SDRAM auto-initialization

∙Self-refresh mode

∙Prioritized refresh

∙Programmable refresh rate and backlog counter

∙Programmable timing parameters

1.3Functional Block Diagram

The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1). Master peripherals, such as the EDMA controller and the CPU can access the DDR2 memory controller through the switched central resource (SCR). The DDR2 memory controller performs all memory-related background tasks such as opening and closing banks, refreshes, and command arbitration.

SPRUF85 –October 2007

DSP DDR2 Memory Controller

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Texas Instruments TMS320C6452 DSP manual Purpose of the Peripheral, Features, Functional Block Diagram

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data Manual Related Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable Bytes Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Self-Refresh Mode Reset ConsiderationsReset Sources DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function Selection Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Offset Acronym Register Description DDR2 Memory Controller Registers DDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register Dmcctl Products Applications DSPRfid