Deactivation Dcab and Deac | Texas Instruments TMS320C6452 DSP

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Peripheral Architecture

2.4.4Deactivation (DCAB and DEAC)

The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command.

Figure 6. DCAB Command

DCAB

DDR_CLK

DDR_CLK

DDR_CKE

DDR_CS

DDR_RAS

DDR_CAS

DDR_WE

DDR_A[13:11, 9:0]

DDR_A[10]

DDR_BA[2:0]

DDR_DQM[3:0]

The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 shows the timings diagram for a DEAC command.

Figure 7. DEAC Command

DEAC

DDR_CLK

DDR_CLK

DDR_CKE

DDR_CS

DDR_RAS

DDR_CAS

DDR_WE

DDR_A[13:11, 9:0]

DDR_A[10]

DDR_BA[2:0]

DDR_DQM[3:0]

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DSP DDR2 Memory Controller

SPRUF85 –October 2007

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Texas Instruments TMS320C6452 DSP manual Deactivation Dcab and Deac, Dcab Command

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference Guides Related Documents From Texas Instruments Related Documents From Texas Instruments Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Mode Register Set MRS and Emrs Refresh ModeDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Activation Actv Ddrcs Ddrras Ddrcas Ddrwe Dcab Command Deactivation Dcab and Deac Read Command DDR2 Read Command Write WRT Command Memory Width and Byte AlignmentAddressable Memory Ranges Memory Width Maximum Addressable Bytes Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level Description Reset Considerations Self-Refresh ModeReset Sources 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Function Selection DDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration SDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description DDR2 Memory Controller Registers Offset Acronym Register Description Module ID and Revision Register Midr DDR2 Memory Controller Status Register DmcstatModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Tsxnr Tsxrd Trtp Tcke Burst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl Rese DSP Products ApplicationsRfid