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Using the DDR2 Memory Controller
Table 12 displays the
Table 12. DDR2 Memory Refresh Specification
Symbol | Description | Value |
tREF | Average Periodic Refresh Interval | 7.8 μs |
Therefore, the value for the
REFRESH_RATE = 266.5 MHz × 7.8 μs = 2078.7 = 81Eh
Table 13 shows the resulting SDRFC configuration.
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| Table 13. SDRFC Configuration |
Field | Value | Function Selection |
SR | 0 | DDR2 memory controller is not in |
REFRESH_RATE | 81Eh | Set to 81Eh DDR2 clock cycles to meet the DDR2 memory refresh rate |
|
| requirement. |
3.2.3Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)
The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification. Table 14 and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along with the data sheet value. These tables also provide a formula to calculate the register field value and displays the resulting calculation. Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1. See Section 4.5 and Section 4.6 for more information.
Table 14. SDTIM1 Configuration
| DDR2 SDRAM Data |
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Register Field | Sheet Parameter |
| Data Sheet | Formula (Register | Field |
Name | Name | Description | Value (nS) | Field Must Be ³) | Value |
T_RFC | tRFC | Refresh cycle time | 127.5 | (tRFC ´ fDDR2_CLK) - 1 | 33 |
T_RP | tRP | Precharge command to refresh | 15 | (tRP ´ fDDR2_CLK) - 1 | 3 |
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| or activate command |
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T_RCD | tRCD | Activate command to | 15 | (tRCD ´ fDDR2_CLK) - 1 | 3 |
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| read/write command |
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T_WR | tWR | Write recovery time | 15 | (tWR ´ fDDR2_CLK) - 1 | 3 |
T_RAS | tRAS | Active to precharge command | 40 | (tRAC ´ fDDR2_CLK) - 1 | 10 |
T_RC | tRC | Activate to Activate command | 55 | (tRC ´ fDDR2_CLK) - 1 | 14 |
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| in the same bank |
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T_RRD | tRRD | Activate to Activate command | 10 | (tRRD ´ fDDR2_CLK) - 1 | 3 |
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| in a different bank |
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T_WTR | tWTR | Write to read command delay | 7.5 | (tWTR ´ fDDR2_CLK) - 1 | 1 |
34 | DSP DDR2 Memory Controller | SPRUF85 |
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