DDR2 Read Command | Texas Instruments TMS320C6452 DSP specification

www.ti.com

Peripheral Architecture

2.4.5READ Command

Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0].

The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or

5.The CAS latency is three cycles in Figure 8. Read latency is equal to CAS latency plus additive latency. The DDR2 memory controller always configures the memory to have an additive latency of 0, so read latency equals CAS latency. Since the default burst size is 8, the DDR2 memory controller returns 8 pieces of data for every read command. If additional accesses are not pending to the DDR2 memory controller, the read burst completes and the unneeded data is disregarded. If additional accesses are pending, depending on the scheduling result, the DDR2 memory controller can terminate the read burst and start a new read burst. Furthermore, the DDR2 memory controller does not issue a DCAB/DEAC command until page information becomes invalid.

Figure 8. DDR2 READ Command

DDR_CLK
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_CAS
DDR_WE
DDR_A[13:0]	COL
DDR_BA[2:0]	BANK
	BANK
DDR_A[10]
DDR_DQM[3:0]
	CAS Latency
DDR_D[31:0]	D0	D1	D2	D3	D4	D5	D6	D7

DDR_DQS[3:0]

SPRUF85 –October 2007

DSP DDR2 Memory Controller

17

Submit Documentation Feedback

Image 17

Texas Instruments TMS320C6452 DSP manual DDR2 Read Command

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data Manual Related Documents From Texas Instruments Related Documents From Texas Instruments Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable Bytes Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Reset Sources Self-Refresh ModeReset Considerations DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function Selection Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Offset Acronym Register Description DDR2 Memory Controller Registers DDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp Tcke Prioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions Rese DDR2 Memory Controller Control Register Dmcctl Rfid Products ApplicationsDSP