Texas Instruments TMS320C6452 DSP specification

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DDR2 Memory Controller Registers

Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)

Bit	Field	Value Description
1-0	T_WTR	These bits specify the minimum number of DDR_CLK cycles from the last write to a read
		command, minus 1. The value for these bits can be derived from the twtr AC timing parameter in the
		DDR2 memory data sheet. Calculate using this formula:
		T_WTR = (twtr/DDR_CLK) - 1

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DSP DDR2 Memory Controller

SPRUF85 –October 2007

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Texas Instruments TMS320C6452 DSP manual DDR2 memory data sheet. Calculate using this formula

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Data Manual Reference Guides Related Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin Description Command Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol Descriptions Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Mode Register Set MRS and EmrsRefresh Mode COL Activation Actv Ddrcs Ddrras Ddrcas Ddrwe Dcab Command Deactivation Dcab and Deac Read Command DDR2 Read Command Addressable Memory Ranges Write WRT CommandMemory Width and Byte Alignment Memory Width Maximum Addressable Bytes Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level Description Self-Refresh Mode Reset ConsiderationsReset Sources DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration 11 DDR2 Sdram Memory Initialization Interrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Function Selection Configuring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 Configuration DDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name Description DDR2 Memory Controller Registers Offset Acronym Register Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Bit Field Value Description Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Trfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Todt Tsxnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Tsxrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl Rese Products Applications DSPRfid