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DDR2 Memory Controller Registers

4.8DDR2 Memory Controller Control Register (DMCCTL)

The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 27 and described in Table 25.

Figure 27. DDR2 Memory Controller Control Register (DMCCTL)

31						16
	Reserved
	R-0x5000
15	6	5	4	3	2	0
		IF
Reserved		RESE	Rsvd	Rsvd		RL
		T
R/W-0x0190		R/W-	R/W- R-0x0			R/W-0x7
		0x1	0x0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 25. DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions

Bit	Field	Value	Description
31-6	Reserved		Reserved. Writes to this register must keep this field at its default value.
15-6	Reserved		Reserved. Writes to this register must keep this field at its default value.
5	IFRESET		DDR2 memory controller interface logic reset. The interface logic controls the signals used to
			communicate with DDR2 SDRAM devices. This bit resets the interface logic. The status of this
			interface logic is shown on the DDR2 memory controller status register.
		0	Release reset.
		1	Assert reset.
4	Reserved		Reserved. Writes to this register must keep this field at its default value.
3	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
2-0	RL		Read latency bits. These bits must be set equal to the CAS latency plus 1.

SPRUF85 –October 2007	DSP DDR2 Memory Controller	45
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Texas Instruments TMS320C6452 DSP manual DDR2 Memory Controller Control Register Dmcctl, Rese

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Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data Manual Related Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Truth Table for DDR2 Sdram Commands DDR2 Sdram CommandsCommand Function Protocol Descriptions Refresh Mode Mode Register Set MRS and EmrsDdrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe COL Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width and Byte Alignment Write WRT CommandAddressable Memory Ranges Memory Width Maximum Addressable Bytes Address Mapping Bank Configuration Register Fields for Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Possible Race Condition Refresh SchedulingRefresh Urgency Levels Urgency Level Description Self-Refresh Mode Reset ConsiderationsReset Sources DDR2 Sdram Mode Register Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Extended Mode Register 1 Configuration 11 DDR2 Sdram Memory Initialization 11.3 DDR2 Sdram Initialization After Register Configuration 11.2 DDR2 Sdram Initialization After ResetInterrupt Support Edma Event Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Sdcfg Configuration Programming the Sdram Configuration Register SdcfgProgramming the Sdram Refresh Control Register Sdrfc Function Selection Sdrfc Configuration DDR2 Memory Refresh SpecificationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration Dmcctl Configuration SDTIM2 ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description Offset Acronym Register Description DDR2 Memory Controller Registers DDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Bit Field Value Description Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Sdram Timing 1 Register SDTIM1 Field Descriptions Sdram Timing 1 Register SDTIM1Trfc TRP Trcd TWR Tras TRC Trrd DDR2 memory data sheet. Calculate using this formula Sdram Timing 2 Register SDTIM2 Field Descriptions Sdram Timing 2 Register SDTIM2Todt Tsxnr Tsxrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register Dmcctl Products Applications DSPRfid