Texas Instruments TMS320C6452 DSP manual List of Figures

	List of Figures
1	DDR2 Memory Controller Block Diagram	10
2	DDR2 Memory Controller Signals	12
3	DDR2 MRS and EMRS Command	14
4	Refresh Command	15
5	ACTV Command	15
6	DCAB Command	16
7	DEAC Command	16
8	DDR2 READ Command	17
9	DDR2 WRT Command	18
10	Byte Alignment	19
11	Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM	19
12	Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM	20
13	Logical Address-to-DDR2 SDRAM Address Map	21
14	DDR2 SDRAM Column, Row, and Bank Access	22
15	DDR2 Memory Controller FIFO Block Diagram	23
16	DDR2 Memory Controller Reset Block Diagram	26
17	Connecting to Two 16-Bit DDR2 SDRAM Devices	30
18	Connecting to a Single 16-Bit DDR2 SDRAM Device	31
19	Connecting to Two 8-Bit DDR2 SDRAM Devices	32
20	Module ID and Revision Register (MIDR)	37
21	DDR2 Memory Controller Status Register (DMCSTAT)	37
22	SDRAM Configuration Register (SDCFG)	38
23	SDRAM Refresh Control Register (SDRFC)	40
24	SDRAM Timing 1 Register (SDTIM1)	41
25	SDRAM Timing 2 Register (SDTIM2)	43
26	Burst Priority Register (BPRIO)	44
27	DDR2 Memory Controller Control Register (DMCCTL)	45

4 List of Figures SPRUF85 –October 2007

Submit Documentation Feedback