Contents | Texas Instruments TMS320C6452 DSP specs

Contents

Preface			6
1	Introduction		9
	1.1	Purpose of the Peripheral	9
	1.2	Features	9
	1.3	Functional Block Diagram	9
	1.4	Industry Standard(s) Compliance Statement	10
2	Peripheral Architecture		11
	2.1	Clock Control	11
	2.2	Memory Map	11
	2.3	Signal Descriptions	11
	2.4	Protocol Description(s)	13
	2.5	Memory Width and Byte Alignment	18
	2.6	Address Mapping	19
	2.7	DDR2 Memory Controller Interface	22
	2.8	Refresh Scheduling	25
	2.9	Self-Refresh Mode	26
	2.10	Reset Considerations	26
	2.11	DDR2 SDRAM Memory Initialization	27
	2.12	Interrupt Support	28
	2.13	EDMA Event Support	28
	2.14	Emulation Considerations	28
3	Using the DDR2 Memory Controller		29
	3.1	Connecting the DDR2 Memory Controller to DDR2 SDRAM	29
	3.2	Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications	33
4	DDR2 Memory Controller Registers		36
	4.1	Module ID and Revision Register (MIDR)	37
	4.2	DDR2 Memory Controller Status Register (DMCSTAT)	37
	4.3	SDRAM Configuration Register (SDCFG)	38
	4.4	SDRAM Refresh Control Register (SDRFC)	40
	4.5	SDRAM Timing 1 Register (SDTIM1)	41
	4.6	SDRAM Timing 2 Register (SDTIM2)	43
	4.7	Burst Priority Register (BPRIO)	44
	4.8	DDR2 Memory Controller Control Register (DMCCTL)	45

SPRUF85 –October 2007

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Texas Instruments TMS320C6452 DSP manual Contents

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Reference Guides Data Manual Related Documents From Texas Instruments Related Documents From Texas Instruments Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function COL Mode Register Set MRS and EmrsRefresh Mode Ddrclk MRS/EMRS Ddrcke Ddrcs Ddrras Ddrcas Ddrwe Ddrcs Ddrras Ddrcas Ddrwe Activation Actv Deactivation Dcab and Deac Dcab Command DDR2 Read Command Read Command Memory Width Maximum Addressable Bytes Write WRT CommandMemory Width and Byte Alignment Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 16-bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels Self-Refresh Mode Reset ConsiderationsReset Sources 11 DDR2 Sdram Memory Initialization 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Function Selection Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter Offset Acronym Register Description DDR2 Memory Controller Registers Bit Field Value Description Module ID and Revision Register MidrDDR2 Memory Controller Status Register Dmcstat Module ID and Revision Register Midr Field Descriptions Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR DDR2 memory data sheet. Calculate using this formula Tsxrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Tsxnr Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise Rese DDR2 Memory Controller Control Register Dmcctl Products Applications DSPRfid