Advantech PCI-1710 user manual Status Register BASE+6 and BASE+7

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GATE External trigger gate function enable bit

Set 1 to enable external trigger gate function, and set 0 to disable.

IRQEN Interrupt enable bit

Set 1 to enable interrupt, and set 0 to disable.

ONE/FH Interrupt source bit

Set 0 to interrupt when an A/D conversion occurs, and set 1 to interrupt when the FIFO is half full.

CNT0 Counter 0 clock source select bit

0 means that the clock source of Counter 0 comes from the internal clock (100 kHz), and 1 means that the clock source of Counter 0 comes from the external clock (maximum up to 10 MHz).

4.8Status Register — BASE+6 and BASE+7

The registers of BASE+6 and BASE+7 provide information for the A/ D configuration and operation.

Table 4-8: Status register

Read

 

 

 

Status Register

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

BASE+7

 

 

 

 

IRQ

F/F

F/H

F/E

 

 

 

 

 

 

 

 

 

BASE+6

 

CNT0

ONE/FH

IRQEN

GATE

EXT

PACER

SW

 

 

 

 

 

 

 

 

 

The content of the status register of BASE+6 is the same as that of the control register.

F/E FIFO Empty flag

This bit indicates whether the FIFO is empty. 1 means that the FIFO is empty.

40 PCI-1710/1710HG User's Manual

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Contents PCI-1710/1710HG Multifunction DAS Card for PCI Bus Http/support.advantech.com Contents Appendix a 82C54 Counter Chip Functions General Information Flexible Inputs Types and Ranges Setting IntroductionPCI-bus Plug and Play On-board Fifo First In First Out MemoryFeatures On-board Programmable CounterSpecifications Analog InputLinearity error ±1 LSB Input impedance 1 GΩ Digital Output Analog OutputDigital Input Programmable Timer/Counter GeneralBlock Diagram PCIInstallation Initial Inspection UnpackingInstallation Instructions Page Signal Connections Pin Assignment I/O ConnectorOverview I/O connector pin assignments for the PCI-1710/1710 HG card Connector Signal Descriptions InputConnector Signal Descriptions part Digital Output signalsSignal Reference Direction Description Name Analog Input Connections Single-ended Channel ConnectionsDifferential Channel Connections Single-ended input channel connectionAignd Differential input channel connection floating signal source Analog Output Connections 10VExternal Trigger Source Connection Trigger Source ConnectionsInternal Pacer Trigger Connection Field Wiring Considerations Page Register Structure and Format I/O Port Address Map Base Read DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Base Write DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Channel Number and A/D Data BASE+0 and BASE+1 Software A/D Trigger BASE+0A/D Channel Range Setting BASE+2 PCI-1710 PCI-1710HG MUX Control-BASE+4 and BASE+5 Example Control Register BASE+6 Status Register BASE+6 and BASE+7 Clear Interrupt and Fifo BASE+8 and BASE+9 10 D/A Output Channel 0 BASE+10 and BASE+11 11 D/A Output Channel 1 BASE+12 and BASE+1312 D/A Reference Control BASE+14 Digital I/O Registers BASE+16 and BASE+17 Read Digital InputCalibration VR Assignment PCL-1710/1710HG VR assignmentA/D Calibration Following list shows the function of each VRD/A Calibration Self A/D Calibration Page 82C54 Counter Chip Functions Counter 1 Intel 82C54Counter Counter Read/Write Control Registers DescriptionRW1 & RW0 STA = Mode 0 Stop on Terminal Count Mode 1 Programmable One-shot PulseMode 2 Rate Generator Counter Operating ModesMode 5 Hardware-Triggered Strobe Mode 3 Square Wave GeneratorMode 4 -Software-Triggered Strobe Read/Write Operation Counter Read-back CommandCounter Operations Counter Latch Operation

PCI-1710 specifications

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