Advantech PCI-1710 user manual Intel 82C54, Counter 1

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A.1 The Intel 82C54

The PCI-1710/1710HG uses one Intel 82C54 compatible programma- ble interval timer/counter chip. The popular 82C54 offers three independent 16-bit counters, counter 0, counter 1 and counter 2. Each counter has a clock input, control gate and an output. You can program each counter for maximum count values from 2 to 65535.

The 82C54 has a maximum input clock frequency of 1 MHz. The PCI-1710/1710HG provides 1 MHz input frequencies to the counter chip from an on-board crystal oscillator.

Counter 0

On the PCI-1710/1710HG, counter 0 can be a 16-bit timer or an event counter, selectable by users. When the clock source is set as an internal source, counter 0 is a 16-bit timer; when set as an external source, then counter 0 is an event counter and the clock source comes from CNT0_CLK. The counter is controlled by CNT0_GATE. When CNT0_GATE input is high, counter 0 will begin to count.

Counter 1 & 2

Counter 1 and counter 2 of the counter chip are cascaded to create a 32-bit timer for the pacer trigger. A low-to-high edge of counter 2 output (PACER_OUT) will trigger an A/D conversion. At the same time, you can use this signal as a synchronous signal for other applications.

52 PCI-1750 User's Manual

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Contents PCI-1710/1710HG Multifunction DAS Card for PCI Bus Http/support.advantech.com Contents Appendix a 82C54 Counter Chip Functions General Information Flexible Inputs Types and Ranges Setting IntroductionPCI-bus Plug and Play On-board Fifo First In First Out MemoryFeatures On-board Programmable CounterSpecifications Analog InputLinearity error ±1 LSB Input impedance 1 GΩ Digital Output Analog OutputDigital Input Programmable Timer/Counter GeneralBlock Diagram PCIInstallation Initial Inspection UnpackingInstallation Instructions Page Signal Connections Pin Assignment I/O ConnectorOverview I/O connector pin assignments for the PCI-1710/1710 HG card Connector Signal Descriptions InputConnector Signal Descriptions part Digital Output signalsSignal Reference Direction Description Name Analog Input Connections Single-ended Channel ConnectionsDifferential Channel Connections Single-ended input channel connectionAignd Differential input channel connection floating signal source Analog Output Connections 10VExternal Trigger Source Connection Trigger Source ConnectionsInternal Pacer Trigger Connection Field Wiring Considerations Page Register Structure and Format I/O Port Address Map Base Read DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Base Write DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Channel Number and A/D Data BASE+0 and BASE+1 Software A/D Trigger BASE+0A/D Channel Range Setting BASE+2 PCI-1710 PCI-1710HG MUX Control-BASE+4 and BASE+5 Example Control Register BASE+6 Status Register BASE+6 and BASE+7 Clear Interrupt and Fifo BASE+8 and BASE+9 10 D/A Output Channel 0 BASE+10 and BASE+11 11 D/A Output Channel 1 BASE+12 and BASE+1312 D/A Reference Control BASE+14 Digital I/O Registers BASE+16 and BASE+17 Read Digital InputCalibration VR Assignment PCL-1710/1710HG VR assignmentA/D Calibration Following list shows the function of each VRD/A Calibration Self A/D Calibration Page 82C54 Counter Chip Functions Counter 1 Intel 82C54Counter Counter Read/Write Control Registers DescriptionRW1 & RW0 STA = Mode 0 Stop on Terminal Count Mode 1 Programmable One-shot PulseMode 2 Rate Generator Counter Operating ModesMode 5 Hardware-Triggered Strobe Mode 3 Square Wave GeneratorMode 4 -Software-Triggered Strobe Read/Write Operation Counter Read-back CommandCounter Operations Counter Latch Operation