Advantech PCI-1710 user manual Control Register BASE+6

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differential, and AI14 is differential, then the scan sequence is AI11, AI12, AI14, AI11, AI12, AI14, AI11…

Warning! Only even channels can be set as differential. An odd channel will become unavailable if its preceding channel is set as differential.

4.7 Control Register — BASE+6

The write-only register BASE+6 allows users to set an A/D trigger source and an interrupt source.

Table 4-7: Control register

Write				Control Register

Bit #	7	6	5		4	3	2	1	0

BASE + 6		CNT0	ONE/FH		IRQEN	GATE	EXT	PACER	SW

SW Software trigger enable bit

Set 1 to enable software trigger, and set 0 to disable.

PACER PACER trigger enable bit

Set 1 to enable pacer trigger, and set 0 to disable.

EXT External trigger enable bit

Set 1 to enable external trigger, and set 0 to disable.

Note! Users cannot enable SW, PACER and EXT concurrently.

Chapter 4 Register Structure and Format

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Contents PCI-1710/1710HG Multifunction DAS Card for PCI Bus Http/support.advantech.com Contents Appendix a 82C54 Counter Chip Functions General Information On-board Fifo First In First Out Memory Flexible Inputs Types and Ranges SettingIntroduction PCI-bus Plug and PlayOn-board Programmable Counter FeaturesAnalog Input SpecificationsLinearity error ±1 LSB Input impedance 1 GΩ Digital Input Analog OutputDigital Output General Programmable Timer/CounterPCI Block DiagramInstallation Unpacking Initial InspectionInstallation Instructions Page Signal Connections Overview I/O ConnectorPin Assignment I/O connector pin assignments for the PCI-1710/1710 HG card Input Connector Signal DescriptionsDigital Output signals Connector Signal Descriptions partSignal Reference Direction Description Name Single-ended Channel Connections Analog Input ConnectionsSingle-ended input channel connection Differential Channel ConnectionsAignd Differential input channel connection floating signal source 10V Analog Output ConnectionsInternal Pacer Trigger Connection Trigger Source ConnectionsExternal Trigger Source Connection Field Wiring Considerations Page Register Structure and Format I/O Port Address Map Base Read DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Base Write DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Software A/D Trigger BASE+0 Channel Number and A/D Data BASE+0 and BASE+1A/D Channel Range Setting BASE+2 PCI-1710 PCI-1710HG MUX Control-BASE+4 and BASE+5 Example Control Register BASE+6 Status Register BASE+6 and BASE+7 Clear Interrupt and Fifo BASE+8 and BASE+9 11 D/A Output Channel 1 BASE+12 and BASE+13 10 D/A Output Channel 0 BASE+10 and BASE+1112 D/A Reference Control BASE+14 Read Digital Input Digital I/O Registers BASE+16 and BASE+17Calibration PCL-1710/1710HG VR assignment VR AssignmentFollowing list shows the function of each VR A/D CalibrationD/A Calibration Self A/D Calibration Page 82C54 Counter Chip Functions Counter Intel 82C54Counter 1 Description Counter Read/Write Control RegistersRW1 & RW0 STA = Counter Operating Modes Mode 0 Stop on Terminal CountMode 1 Programmable One-shot Pulse Mode 2 Rate GeneratorMode 4 -Software-Triggered Strobe Mode 3 Square Wave GeneratorMode 5 Hardware-Triggered Strobe Counter Operations Counter Read-back CommandRead/Write Operation Counter Latch Operation