Advantech PCI-1710 user manual 10 D/A Output Channel 0 BASE+10 and BASE+11

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4.10D/A Output Channel 0 — BASE+10 and BASE+11

The write-only registers of BASE+10 and BASE+11 accept data for D/A Channel 0 output.

Table 4-10: Registers for D/A channel 0 data

Write				D/A Output Channel

Bit #	7	6	5		4	3	2	1	0

BASE+11						DA11	DA10	DA9	DA8

BASE+10	DA7	DA6	DA5		DA4	DA3	DA2	DA1	DA0

DA11 ~ DA0 Digital to Analog data

DA0 is the LSB and DA11 is the MSB of the D/A data.

4.11D/A Output Channel 1 — BASE+12 and BASE+13

The write-only registers of BASE+12 and BASE+13 accept data for the D/A channel 1 output.

Table 5-11: Registers for D/A channel 1 data

Write				D/A Output Channel

Bit #	7	6	5		4	3	2	1	0

BASE+13						DA11	DA10	DA9	DA8

BASE+12	DA7	DA6	DA5		DA4	DA3	DA2	DA1	DA0

DA11 ~ DA0 Digital to Analog data

DA0 is the LSB and DA11 is the MSB of the D/A data.

42 PCI-1710/1710HG User's Manual

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Contents PCI-1710/1710HG Multifunction DAS Card for PCI Bus Http/support.advantech.com Contents Appendix a 82C54 Counter Chip Functions General Information PCI-bus Plug and Play Flexible Inputs Types and Ranges SettingIntroduction On-board Fifo First In First Out MemoryFeatures On-board Programmable CounterSpecifications Analog InputLinearity error ±1 LSB Input impedance 1 GΩ Digital Input Analog OutputDigital Output Programmable Timer/Counter GeneralBlock Diagram PCIInstallation Initial Inspection UnpackingInstallation Instructions Page Signal Connections Overview I/O ConnectorPin Assignment I/O connector pin assignments for the PCI-1710/1710 HG card Connector Signal Descriptions InputConnector Signal Descriptions part Digital Output signalsSignal Reference Direction Description Name Analog Input Connections Single-ended Channel ConnectionsDifferential Channel Connections Single-ended input channel connectionAignd Differential input channel connection floating signal source Analog Output Connections 10VInternal Pacer Trigger Connection Trigger Source ConnectionsExternal Trigger Source Connection Field Wiring Considerations Page Register Structure and Format I/O Port Address Map Base Read DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Base Write DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Channel Number and A/D Data BASE+0 and BASE+1 Software A/D Trigger BASE+0A/D Channel Range Setting BASE+2 PCI-1710 PCI-1710HG MUX Control-BASE+4 and BASE+5 Example Control Register BASE+6 Status Register BASE+6 and BASE+7 Clear Interrupt and Fifo BASE+8 and BASE+9 10 D/A Output Channel 0 BASE+10 and BASE+11 11 D/A Output Channel 1 BASE+12 and BASE+1312 D/A Reference Control BASE+14 Digital I/O Registers BASE+16 and BASE+17 Read Digital InputCalibration VR Assignment PCL-1710/1710HG VR assignmentA/D Calibration Following list shows the function of each VRD/A Calibration Self A/D Calibration Page 82C54 Counter Chip Functions Counter Intel 82C54Counter 1 Counter Read/Write Control Registers DescriptionRW1 & RW0 STA = Mode 2 Rate Generator Mode 0 Stop on Terminal CountMode 1 Programmable One-shot Pulse Counter Operating ModesMode 4 -Software-Triggered Strobe Mode 3 Square Wave GeneratorMode 5 Hardware-Triggered Strobe Counter Operations Counter Read-back CommandRead/Write Operation Counter Latch Operation