SUPER MICRO Computer X8SIL user manual Sgpio 0/1 Headers, Alarm Reset

X8SIL/X8SIL-F User's Manual

T-SGPIO 0/1 Headers

Two T-SGPIO (Serial-Link General Pur-

Serial_Link-SGPIO

Pin Definitions

pose Input/Output) headers are located near the SATA connectors on the moth- erboard. These headers are used to communicate with the enclosure manage- ment chip in the system. See the table on

Pin#

1

3

5

7

Definition

NC

Ground

Load

Clock

Pin Definition

2 NC

4 DATA Out

6Ground

8NC

the right for pin definitions. Refer to the board layout below for the locations of the headers.

NC: No Connections

Alarm Reset

If three power supplies are installed and Alarm Reset (JAR) is connected, the sys- tem will notify you when any of the three power modules fail. Connect JAR to a micro-switch to turn off the alarm that is activated when a power module fails. See the table on the right for pin definitions.

KB/MOUSE		JPI2C:PWR I2C	JPI2C
			FLOPPY
	JPUSB1
COM1	JAR	JAR:PSU ALARM RST

Alarm Reset
Pin Definitions
Pin Setting	Definition
Pin 1	Ground
Pin 2	+5V

	A. T-SGPIO 0
DIMM1BDIMM2BDIMM1A DIMM2A UDIMM/RDIMM1066/1333DDR3 required	B. T-SGPIO 1
	C. Alarm Reset

VGA	C
	FAN5
	JLAN1
	LAN1
	JLAN2
JPB JPL1 JPL2	JI2C1
	JI2C2

J6

SLOT7 PCI-E X8 GEN2

FAN1
FAN2
	JLED1:Power LED	JD1:Buzzer/Speaker
SPKR1	JLED1	JD1
CPU
JF1
		JF1

J5

SLOT6 PCI-E X8 GEN2

LE7	J8	REV:1.00	USA
	SLOT5 PCI-E X4 on X8		IN
		X8SIL DESIGNED
	SLOT4 PCI 33MHZ

COM2	JL1:CHASSIS INTRUSION	USB 10/11
	JL1JPG1

						LE4	FAN3
						LE3
MAC CODE	LE2	JBT1				T-SGPIO2
BAR CODE	JBT1:CMOS CLEAR					SGPIO1-T	JPT1
	I-SATA5		I-SATA1		I-SATA3
		I-SATA4		I-SATA0		I-SATA2
USB4	USB2/3						FAN4

B

A

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