Chapter 4: BIOS
Thermal Management 2 (Available if supported by the CPU.)
Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage and frequency when the CPU temperature reaches a predefined overheat threshold. Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be regulated via CPU Internal Clock modulation when the CPU temperature reaches the overheat threshold. The options are Disabled and Enabled.
C1 Enhanced Mode (Available when supported by the CPU.)
Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to prevent overheat. The options are Enabled and Disabled. (Note: please refer to Intel’s web site for detailed information.)
Execute Disable Bit (Available when supported by the CPU.)
Set to Enabled to allow the processor to classify areas in memory where an application code can execute and where it cannot, and thus preventing a worm or a virus from inserting and creating a flood of codes to overwhelm the processor or damage the system during an attack. (Note: this feature is available when your OS and your CPU support the function of Execute Disable Bit.) The options are Disabled and Enabled. (Note: For more information regarding hardware/software support for this function, please refer to Intel's and Microsoft's web sites.)
Adjacent Cache Line Prefetch (Available when supported by the CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The CPU fetches both cache lines for 128 bytes as comprised if Enabled. The default settings are Disabled for the Intel 5100 Series Processors and Enable for the 5000 Series Processors.
Hardware Prefetcher (Available when supported by the CPU.)
Set to Enabled to activate the hardware components that are used in conjunction with software programs to prefetch data in order to shorten execution cycles and maximize data processing efficiency. The options are Disabled and Enabled.
Direct Cache Access (Available when supported by the CPU.)
Set to Enable to route inbound network IO traffic directly into processor caches to reduce memory latency and improve network performance. The options are Enabled and Disabled. If this item is set to Enabled, the following item will display.
DCA Delay Clocks (Available if supported by the CPU.)
This feature allows the user to set the clock delay setting from snoop to prefetch for Direct Cache Access. Select a setting from 8 (bus cycles) to 120 (bus cycles) (in