SUPER MICRO Computer H8QG6+-F, H8QGI+-F user manual ECC Configuration

Chapter 4: BIOS

Power Down Mode

This sets the DDR power down mode. Options are Auto, Channel and Chip Select.

DRAM Parity Enable

This sets the DRAM Parity Enable to either Auto, Enabled and Disabled.

Bank Swizzle Mode

This sets the Bank Swizzle Mode to either Auto, Enabled and Disabled.

ECC Configuration

ECC Mode

This submenu sets the level of ECC protection. Options include Disabled, Basic, Good, Super, Max and User. Selecting User activates the other op- tions for user setting.

Note: The "Super" ECC mode dynamically sets the DRAM scrub rate so all of memory is scrubbed in 8-hours.

DRAM ECC Enable

This setting allows hardware to report and correct memory errors automati- cally, maintaining system integrity. Options are Enabled or Disabled.

DRAM Scrub Redirect

This setting allows the system to correct DRAM ECC errors immediately when they occur, even if background scrubbing is off. Options are Enabled or Disabled.

4-Bit ECC Mode

Allows the user to enabled 4-bit ECC mode (also known as ECC Chipkill). Options are Enabled and Disabled.

DRAM BG Scrub

Corrects memory errors so later reads are correct. Options are Disabled and various times in nanoseconds and microseconds. The default is 163.8us.

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