
Appendix B: BIOS POST Checkpoint Codes
B-3  Uncompressed Initialization Codes
The following runtime checkpoint codes are listed in order of execution. These codes are uncompressed in F0000h shadow RAM.
| Checkpoint | Code Description | 
| 03h | The NMI is disabled. Next, checking for a soft reset or a power on condition. | 
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| 05h | The BIOS stack has been built. Next, disabling cache memory. | 
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| 06h | Uncompressing the POST code next. | 
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| 07h | Next, initializing the CPU and the CPU data area. | 
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| 08h | The CMOS checksum calculation is done next. | 
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| 0Ah | The CMOS checksum calculation is done. Initializing the CMOS status register for date and | 
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 | time next. | 
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| 0Bh | The CMOS status register is initialized. Next, performing any required initialization before the | 
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 | keyboard BAT command is issued. | 
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| 0Ch | The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboard | 
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 | controller. | 
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| 0Eh | The keyboard controller BAT command result has been verified. Next, performing any | 
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 | necessary initialization after the keyboard controller BAT command test. | 
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| 0Fh | The initialization after the keyboard controller BAT command test is done. The keyboard | 
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 | command byte is written next. | 
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| 10h | The keyboard controller command byte is written. Next, issuing the Pin 23 and 24 blocking and | 
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 | unblocking command. | 
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| 11h | Next, checking if <End or <Ins> keys were pressed during power on. Initializing CMOS RAM | 
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 | if the Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the | 
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 | <End> key was pressed. | 
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| 12h | Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2. | 
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| 13h | The video display has been disabled. Port B has been initialized. Next, initializing the chipset. | 
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| 14h | The 8254 timer test will begin next. | 
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| 19h | Next, programming the flash ROM. | 
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| 1Ah | The memory refresh line is toggling. Checking the 15 second on/off time next. | 
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| 2Bh | Passing control to the video ROM to perform any required configuration before the video ROM | 
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 | test. | 
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| 2Ch | All necessary processing before passing control to the video ROM is done. Looking for the | 
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 | video ROM next and passing control to it. | 
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| 2Dh | The video ROM has returned control to BIOS POST. Performing any required processing after | 
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 | the video ROM had control | 
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| 23h | Reading the 8042 input port and disabling the MEGAKEY Green PC feature next. Making the | 
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 | BIOS code segment writable and performing any necessary configuration before initializing the | 
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 | interrupt vectors. | 
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| 24h | The configuration required before interrupt vector initialization has completed. Interrupt vector | 
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 | initialization is about to begin. | 
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| 25h | Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on. | 
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| 27h | Any initialization before setting video mode will be done next. | 
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| 28h | Initialization before setting the video mode is complete. Configuring the monochrome mode and | 
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 | color mode settings next. | 
| 2Ah | Bus initialization system, static, output devices will be done next, if present. See the last page | 
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 | for additional information. | 
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