Cypress CY62138CV30 Thermal Resistance, AC Test Loads and Waveforms, Data Retention Waveform

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CY62138FV30 MoBL®

Thermal Resistance [8]

Parameter

Description

Test Conditions

SOIC

VFBGA

TSOP II

STSOP

TSOP I

Unit

ΘJA

Thermal Resistance

Still air, soldered on a 3 x 4.5

44.53

38.49

44.16

59.72

50.19

°C/W

 

(Junction to Ambient)

inch, two layer printed circuit

 

 

 

 

 

 

 

 

board

 

 

 

 

 

 

ΘJC

Thermal Resistance

24.05

17.66

11.97

15.38

14.59

°C/W

 

 

(Junction to Case)

 

 

 

 

 

 

 

AC Test Loads and Waveforms

R1

VCC

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

 

 

VCC

 

 

 

 

 

 

 

 

 

 

10%

 

 

 

 

 

90%

R2

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise Time = 1 V/ns

 

 

 

 

 

 

 

Equivalent to:

THEVENIN EQUIVALENT

OUTPUT

 

 

 

RTH

 

 

 

 

V

 

 

 

 

 

 

 

90%

10%

Fall Time = 1 V/ns

Parameters

2.5V (2.2V to 2.7V)

3.0V (2.7V to 3.6V)

Unit

R1

16667

1103

 

 

 

 

R2

15385

1554

 

 

 

 

RTH

8000

645

VTH

1.20

1.75

V

Data Retention Characteristics (Over the Operating Range)

Parameter

Description

Conditions

Min

Typ [3]

Max

Unit

VDR

VCC for Data Retention

 

1.5

 

 

V

ICCDR [7]

Data Retention Current

VCC = 1.5V,

 

1

4

A

 

 

CE1 > VCC 0.2V or CE2 < 0.2V,

 

 

 

 

 

 

VIN > VCC 0.2V or VIN < 0.2V

 

 

 

 

tCDR [8]

Chip Deselect to Data Retention Time

 

0

 

 

ns

tR [9]

Operation Recovery Time

 

tRC

 

 

ns

Data Retention Waveform [10]

 

 

VCC(min)

DATA RETENTION MODE

VCC(min)

V

CC

V

> 1.5V

 

tCDR

DR

 

tR

 

 

 

 

CE

 

 

 

 

Notes:

9.Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.

10.CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.

Document #: 001-08029 Rev. *E

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Contents Logic Block Diagram Functional Description FeaturesCypress Semiconductor Corporation Pin Configuration Product PortfolioElectrical Characteristics Over the Operating Range Maximum RatingsProduct Range Ambient Parameter Description Test Conditions Max UnitData Retention Characteristics Over the Operating Range Thermal ResistanceAC Test Loads and Waveforms Data Retention WaveformRead Cycle Parameter Description 45 ns Unit MinWrite Cycle Read Cycle No OE controlled 10, 16 Switching WaveformsWrite Cycle No WE controlled 10, 14, 18 Inputs/Outputs Mode Power Truth TablePackage Diagrams Ordering InformationPin Tsop II Pin 450 Mil Molded Soic Pin Tsop I 8 x 20 mm Pin Stsop 8 x 13.4 mm Issue Orig. Description of Change Date Document History

CY62138CV25, CY62138CV30, CY62138FV30, CY62138CV33 specifications

The Cypress CY62138 series, which includes the CY62138CV30, CY62138CV33, CY62138CV25, and CY62138FV30, represents a family of high-performance CMOS Static Random Access Memory (SRAM) devices. These components are widely utilized in various applications due to their speed, density, and reliability.

One of the key features of the CY62138 series is its memory density. These SRAMs provide 2Megwords x 8Bit (2M x 8) configurations, making them suitable for applications that require substantial memory capacity without the complexities associated with dynamic RAM technologies. The components are built using advanced CMOS technology, which enables low power consumption while maintaining high-speed performance.

The devices in this series operate under a voltage range of 2.7V to 3.6V for the CY62138CV models and can operate at clock speeds of 30ns, 33ns, and 25ns, depending on the specific variant. The CY62138FV30 variant, optimized for fast operation, can achieve access times as low as 30ns. This speed is particularly advantageous in applications such as buffering, caching, and other scenarios where rapid data access is critical.

Another prominent feature is the CY62138 series' support for a straightforward interface, which simplifies design integration. The SRAMs boast a asynchronous operation that eliminates the need for complex timing requirements, thereby easing the design process for engineers. The devices support both byte and word access modes, providing flexibility in handling data.

In terms of reliability, the CY62138 SRAMs are designed to operate over an extensive temperature range, making them suitable for harsh environments. They also feature a write protection mechanism, ensuring that data integrity is maintained during unexpected power fluctuations.

In summary, the Cypress CY62138 series combines high density, rapid access times, low power consumption, and robust reliability features, making it a highly effective choice for a wide range of applications, including telecommunications, industrial control systems, and consumer electronics. As technology evolves, devices from this series continue to meet the demands for reliable, high-speed memory solutions in various sectors.