Cypress CY62138CV25, CY62138CV30, CY62138CV33, CY62138FV30 Pin Configuration, Product Portfolio

Page 2

CY62138FV30 MoBL®

Pin Configuration [2]

36-Ball VFBGA

Top View

32-Pin SOIC/TSOP II

Top View

A0

A1

CE2

A3

A6

A8

A

IO4

A2

 

 

 

 

A4

A7

IO0

B

WE

IO5

 

 

 

NC

A5

 

IO1

C

VSS

 

 

 

 

 

 

 

 

VCC

D

V

 

 

 

 

 

 

 

 

VSS

E

CC

 

 

 

 

 

 

 

 

 

 

IO6

 

 

 

NC

A17

 

IO 2

F

 

 

 

 

 

 

A16

 

 

 

IO7

 

 

 

CE

A15

IO 3

G

OE

 

1

A9

A10

 

A11

A12

A13

A14

H

A17

A16

A14

A12

A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCC

A15

CE2

WE

A13

A8

A9

A11

OE

A10

CE1

IO7

IO6

IO5

IO4

IO3

A11

 

1

 

32

 

 

OE

 

A9

 

2

 

31

 

 

A10

A8

 

3

 

30

 

 

CE1

A13

 

4

 

29

 

 

IO7

WE

 

5

 

28

 

 

IO6

CE2

 

6

TSOP I

27

 

 

IO5

A15

 

7

26

 

 

IO

VCC

 

8

Top View

25

 

 

IO34

 

 

 

 

 

A17

 

9

(not to scale)

24

 

 

GND

A16

 

10

 

23

 

 

IO2

A14

 

11

 

22

 

 

IO1

 

 

 

 

 

 

 

 

A12

 

12

 

21

 

 

IO0

A7

 

13

 

20

 

 

A0

 

 

 

 

A6

 

14

 

19

 

 

A1

 

 

 

 

A5

 

15

 

18

 

 

A2

A4

 

16

 

17

 

 

A3

 

 

 

 

 

A11

 

25

 

24

 

 

OE

 

 

 

 

 

 

A9

 

26

 

23

 

 

A10

 

 

 

A8

 

27

 

22

 

 

CE1

A13

 

28

 

21

 

 

IO7

WE

 

29

 

20

 

 

IO6

CE2

 

30

STSOP

19

 

 

IO5

A15

 

31

18

 

 

IO4

VCC

 

32

Top View

17

 

 

IO3

 

 

 

 

A17

 

1

(not to scale)

16

 

 

GND

A16

 

2

 

15

 

 

IO2

A14

 

3

 

14

 

 

IO1

 

 

 

 

A12

 

4

 

13

 

 

IO0

A7

 

5

 

12

 

 

A0

 

 

 

 

A6

 

6

 

11

 

 

A1

 

 

 

 

A5

 

7

 

10

 

 

A2

A4

 

8

 

9

 

 

A3

 

 

 

 

 

Product Portfolio

 

 

 

 

 

 

 

 

 

Power Dissipation

 

 

 

 

VCC Range (V)

 

 

 

 

 

 

 

 

Product

 

 

Speed

 

Operating ICC (mA)

 

 

Standby ISB2 (A)

 

 

 

 

 

(ns)

f = 1 MHz

f = fmax

 

 

 

 

 

 

 

 

 

 

 

 

Min

 

Typ [3]

 

Max

 

Typ [3]

Max

Typ [3]

Max

 

Typ [3]

Max

CY62138FV30LL

2.2

 

3.0

 

3.6

45

1.6

2.5

13

18

 

1

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

2.NC pins are not connected on the die.

3.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.

Document #: 001-08029 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description Pin Configuration Product PortfolioProduct Range Ambient Electrical Characteristics Over the Operating RangeMaximum Ratings Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms Data Retention Characteristics Over the Operating RangeThermal Resistance Data Retention WaveformWrite Cycle Parameter Description 45 ns Unit MinRead Cycle Write Cycle No WE controlled 10, 14, 18 Switching WaveformsRead Cycle No OE controlled 10, 16 Inputs/Outputs Mode Power Truth TablePackage Diagrams Ordering InformationPin Tsop II Pin 450 Mil Molded Soic Pin Tsop I 8 x 20 mm Pin Stsop 8 x 13.4 mm Issue Orig. Description of Change Date Document History

CY62138CV25, CY62138CV30, CY62138FV30, CY62138CV33 specifications

The Cypress CY62138 series, which includes the CY62138CV30, CY62138CV33, CY62138CV25, and CY62138FV30, represents a family of high-performance CMOS Static Random Access Memory (SRAM) devices. These components are widely utilized in various applications due to their speed, density, and reliability.

One of the key features of the CY62138 series is its memory density. These SRAMs provide 2Megwords x 8Bit (2M x 8) configurations, making them suitable for applications that require substantial memory capacity without the complexities associated with dynamic RAM technologies. The components are built using advanced CMOS technology, which enables low power consumption while maintaining high-speed performance.

The devices in this series operate under a voltage range of 2.7V to 3.6V for the CY62138CV models and can operate at clock speeds of 30ns, 33ns, and 25ns, depending on the specific variant. The CY62138FV30 variant, optimized for fast operation, can achieve access times as low as 30ns. This speed is particularly advantageous in applications such as buffering, caching, and other scenarios where rapid data access is critical.

Another prominent feature is the CY62138 series' support for a straightforward interface, which simplifies design integration. The SRAMs boast a asynchronous operation that eliminates the need for complex timing requirements, thereby easing the design process for engineers. The devices support both byte and word access modes, providing flexibility in handling data.

In terms of reliability, the CY62138 SRAMs are designed to operate over an extensive temperature range, making them suitable for harsh environments. They also feature a write protection mechanism, ensuring that data integrity is maintained during unexpected power fluctuations.

In summary, the Cypress CY62138 series combines high density, rapid access times, low power consumption, and robust reliability features, making it a highly effective choice for a wide range of applications, including telecommunications, industrial control systems, and consumer electronics. As technology evolves, devices from this series continue to meet the demands for reliable, high-speed memory solutions in various sectors.