Cypress CY62136EV30 manual Switching Waveforms 14, Read Cycle 1 Address Transition Controlled14

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CY62136EV30

MoBL®

Switching Waveforms [14, 15]

Read Cycle 1 (Address Transition Controlled)[14, 15]

tRC

ADDRESS

tOHA tAA

DATA OUT

PREVIOUS DATA VALID

 

 

 

 

DATA VALID

 

 

 

 

 

 

 

 

 

 

Read Cycle No. 2 (OE Controlled)[15, 16]

ADDRESS

 

 

CE

 

tRC

 

 

 

 

tPD

 

t

tHZCE

OE

ACE

 

 

 

 

tDOE

tHZOE

BHE/BLE

 

tLZOE

 

 

tDBE

tHZBE

 

 

 

tLZBE

HIGH

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

tLZCE

DATA VALID

 

 

VCC

tPU

ICC

50%

SUPPLY

50%

CURRENT

 

ISB

Notes:

14.The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

15.WE is HIGH for read cycle.

16.Address valid prior to or coincident with CE and BHE, BLE transition LOW.

Document #: 38-05569 Rev. *B

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Contents Features Logic Block DiagramCypress Semiconductor Corporation Vfbga Top View Tsop II Top View Pin Configuration2Product Portfolio4 MaxElectrical Characteristics Over the Operating Range 5, 6 Maximum RatingsOperating Range7 AC Test Loads and Waveforms Data Retention Characteristics Over the Operating Range8Thermal Resistance8 Data Retention Waveform45 ns Parameter Description Unit Min Max Read Cycle Write CycleSwitching Waveforms 14 Read Cycle 1 Address Transition Controlled14Read Cycle No OE Controlled15 Write Cycle No WE Controlled13, 17 Write Cycle No CE Controlled13, 17Data I/O Write Cycle No WE Controlled, OE LOW18 Write Cycle No BHE/BLE Controlled, OE LOW18DATAI/O Data Ordering Information Inputs/Outputs Mode PowerOrdering Code Package Package Type Operating Diagram Range BHE BLEPackage Diagrams Pin Vfbga 6 x 8 x 1 mmPin Tsop II Issue Date Orig. Description of Change Document HistoryREV ECN no