Cypress CY62136EV30 manual Package Diagrams, Pin Vfbga 6 x 8 x 1 mm

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CY62136EV30

MoBL®

Package Diagrams

TOP VIEW

BOTTOM VIEW

A1 CORNER

8.00±0.10

A1 CORNER

1 2 3 4 5 6

8.00±0.10

5.25

0.75

2.625

Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X)

6 5 4 3 2 1

6.00±0.10

0.21±0.05

SEATING PLANE

0.10 C

0.15(4X)

1.875

0.75

3.75

6.00±0.10

51-85150-*D

0.26 MAX.	C
	1.00 MAX

Document #: 38-05569 Rev. *B

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation Vfbga Top View Tsop II Top View Pin Configuration2Product Portfolio4 MaxMaximum Ratings Electrical Characteristics Over the Operating Range 5, 6Operating Range7 AC Test Loads and Waveforms Data Retention Characteristics Over the Operating Range8Thermal Resistance8 Data Retention Waveform45 ns Parameter Description Unit Min Max Read Cycle Write CycleRead Cycle 1 Address Transition Controlled14 Switching Waveforms 14Read Cycle No OE Controlled15 Write Cycle No CE Controlled13, 17 Write Cycle No WE Controlled13, 17Data I/O Write Cycle No BHE/BLE Controlled, OE LOW18 Write Cycle No WE Controlled, OE LOW18DATAI/O Data Ordering Information Inputs/Outputs Mode PowerOrdering Code Package Package Type Operating Diagram Range BHE BLEPackage Diagrams Pin Vfbga 6 x 8 x 1 mmPin Tsop II Document History Issue Date Orig. Description of ChangeREV ECN no